DE69023423D1 - Masken-ROM-Herstellungsverfahren. - Google Patents

Masken-ROM-Herstellungsverfahren.

Info

Publication number
DE69023423D1
DE69023423D1 DE69023423T DE69023423T DE69023423D1 DE 69023423 D1 DE69023423 D1 DE 69023423D1 DE 69023423 T DE69023423 T DE 69023423T DE 69023423 T DE69023423 T DE 69023423T DE 69023423 D1 DE69023423 D1 DE 69023423D1
Authority
DE
Germany
Prior art keywords
manufacturing process
mask rom
rom manufacturing
mask
rom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69023423T
Other languages
English (en)
Other versions
DE69023423T2 (de
Inventor
Yasuo Naruke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69023423D1 publication Critical patent/DE69023423D1/de
Publication of DE69023423T2 publication Critical patent/DE69023423T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/383—Channel doping programmed

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Memories (AREA)
DE69023423T 1989-08-18 1990-08-17 Masken-ROM-Herstellungsverfahren. Expired - Fee Related DE69023423T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1212522A JP2509706B2 (ja) 1989-08-18 1989-08-18 マスクｒｏｍの製造方法

Publications (2)

Publication Number Publication Date
DE69023423D1 true DE69023423D1 (de) 1995-12-14
DE69023423T2 DE69023423T2 (de) 1996-04-25

Family

ID=16624065

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69023423T Expired - Fee Related DE69023423T2 (de) 1989-08-18 1990-08-17 Masken-ROM-Herstellungsverfahren.

Country Status (4)

Country Link
US (1) US5002896A (de)
EP (1) EP0413353B1 (de)
JP (1) JP2509706B2 (de)
DE (1) DE69023423T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2509707B2 (ja) * 1989-09-04 1996-06-26 株式会社東芝 半導体装置の製造方法
KR960010736B1 (ko) * 1991-02-19 1996-08-07 미쓰비시뎅끼 가부시끼가이샤 마스크 rom 및 그 제조방법
JP2689031B2 (ja) * 1991-04-01 1997-12-10 三菱電機株式会社 半導体記憶装置およびその製造方法
JP3109537B2 (ja) * 1991-07-12 2000-11-20 日本電気株式会社 読み出し専用半導体記憶装置
JP3043135B2 (ja) * 1991-09-26 2000-05-22 新日本製鐵株式会社 不揮発性半導体メモリの製造方法
JPH05102436A (ja) * 1991-10-09 1993-04-23 Ricoh Co Ltd 半導体メモリ装置とその製造方法
US5236853A (en) * 1992-02-21 1993-08-17 United Microelectronics Corporation Self-aligned double density polysilicon lines for ROM and EPROM
JP2842066B2 (ja) * 1992-08-03 1998-12-24 日本電気株式会社 固体撮像装置及びその製造方法
US5264386A (en) * 1992-09-08 1993-11-23 United Microelectronics Corporation Read only memory manufacturing method
JP3695539B2 (ja) * 1993-02-01 2005-09-14 ナショナル・セミコンダクター・コーポレイション 超高密度交互金属仮想接地ｒｏｍ、ならびにその読み出し方法及びその製造方法
US5378647A (en) * 1993-10-25 1995-01-03 United Microelectronics Corporation Method of making a bottom gate mask ROM device
US5330924A (en) * 1993-11-19 1994-07-19 United Microelectronics Corporation Method of making 0.6 micrometer word line pitch ROM cell by 0.6 micrometer technology
US5514610A (en) * 1995-03-17 1996-05-07 Taiwan Semiconductor Manufacturing Company Method of making an optimized code ion implantation procedure for read only memory devices
US5585298A (en) * 1995-03-31 1996-12-17 Eastman Kodak Company Self aligned antiblooming structure for solid state image sensors
US5585297A (en) * 1995-05-25 1996-12-17 United Microelectronics Corporation Method of manufacture of multi-state mask ROM and multi-state mask ROM device produced thereby
US5589414A (en) * 1995-06-23 1996-12-31 Taiwan Semiconductor Manufacturing Company Ltd. Method of making mask ROM with two layer gate electrode
US5538914A (en) * 1995-08-03 1996-07-23 Taiwan Semiconductor Manufacturing Company LDD method of coding mask ROM device and LDD coded mask ROM device produced thereby
US6853587B2 (en) 2002-06-21 2005-02-08 Micron Technology, Inc. Vertical NROM having a storage density of 1 bit per 1F2
US6873550B2 (en) 2003-08-07 2005-03-29 Micron Technology, Inc. Method for programming and erasing an NROM cell
US6830963B1 (en) 2003-10-09 2004-12-14 Micron Technology, Inc. Fully depleted silicon-on-insulator CMOS logic
US7202523B2 (en) 2003-11-17 2007-04-10 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
US7157769B2 (en) 2003-12-18 2007-01-02 Micron Technology, Inc. Flash memory having a high-permittivity tunnel dielectric
US7221018B2 (en) 2004-02-10 2007-05-22 Micron Technology, Inc. NROM flash memory with a high-permittivity gate dielectric
US6952366B2 (en) 2004-02-10 2005-10-04 Micron Technology, Inc. NROM flash memory cell with integrated DRAM
US7274068B2 (en) 2004-05-06 2007-09-25 Micron Technology, Inc. Ballistic direct injection NROM cell on strained silicon structures
US20050274994A1 (en) * 2004-06-14 2005-12-15 Rhodes Howard E High dielectric constant spacer for imagers
CN101506942B (zh) * 2007-10-22 2011-05-18 香港应用科技研究院有限公司 可记录电存储器的制作

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5559759A (en) * 1978-10-27 1980-05-06 Hitachi Ltd Semiconductor device
JPS5768069A (en) * 1980-10-14 1982-04-26 Fujitsu Ltd Manufacture of semiconductor device
JPS5836508B2 (ja) * 1980-12-25 1983-08-09 富士通株式会社 半導体装置の製造方法
JPS57130463A (en) * 1981-02-06 1982-08-12 Toshiba Corp Semiconductor memory
JPS5885566A (ja) * 1981-11-16 1983-05-21 Toshiba Corp 電荷結合デバイスの製造方法
FR2533371B1 (fr) * 1982-09-21 1985-12-13 Thomson Csf Structure de grille pour circuit integre comportant des elements du type grille-isolant-semi-conducteur et procede de realisation d'un circuit integre utilisant une telle structure
NL8301629A (nl) * 1983-05-09 1984-12-03 Philips Nv Halfgeleiderinrichting.
JPS59107564A (ja) * 1983-11-09 1984-06-21 Hitachi Ltd 半導体装置
JPS60182763A (ja) * 1984-02-29 1985-09-18 Nec Corp 集積回路装置およびその製造方法
JPS59210663A (ja) * 1984-04-16 1984-11-29 Hitachi Ltd 半導体メモリ装置
JPS61152060A (ja) * 1984-12-26 1986-07-10 Hitachi Ltd 半導体装置
JPS6271273A (ja) * 1985-09-24 1987-04-01 Nec Corp 電荷結合素子の製造方法
US4774203A (en) * 1985-10-25 1988-09-27 Hitachi, Ltd. Method for making static random-access memory device
JPH0797606B2 (ja) * 1986-10-22 1995-10-18 株式会社日立製作所 半導体集積回路装置の製造方法
US4742016A (en) * 1987-03-30 1988-05-03 Eastman Kodak Company Method of manufacture of a two-phase CCD
JP2555103B2 (ja) * 1987-11-13 1996-11-20 株式会社日立製作所 半導体集積回路装置の製造方法
JPH0280357A (ja) * 1988-09-16 1990-03-20 Kubota Ltd 無機質製品の押出成形用配合物

Also Published As

Publication number Publication date
JPH0376266A (ja) 1991-04-02
DE69023423T2 (de) 1996-04-25
JP2509706B2 (ja) 1996-06-26
EP0413353B1 (de) 1995-11-08
US5002896A (en) 1991-03-26
EP0413353A3 (en) 1991-06-12
EP0413353A2 (de) 1991-02-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee