DE68928840D1 - Synchroner dynamischer Speicher - Google Patents

Synchroner dynamischer Speicher

Info

Publication number
DE68928840D1
DE68928840D1 DE68928840T DE68928840T DE68928840D1 DE 68928840 D1 DE68928840 D1 DE 68928840D1 DE 68928840 T DE68928840 T DE 68928840T DE 68928840 T DE68928840 T DE 68928840T DE 68928840 D1 DE68928840 D1 DE 68928840D1
Authority
DE
Germany
Prior art keywords
dynamic memory
synchronous dynamic
synchronous
memory
dynamic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68928840T
Other languages
English (en)
Other versions
DE68928840T2 (de
Inventor
Roy Edward Harlin
Richard Arthur Herrington
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/277,637 external-priority patent/US5142637A/en
Priority claimed from US07/278,333 external-priority patent/US5148523A/en
Priority claimed from US07/277,687 external-priority patent/US5148524A/en
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE68928840D1 publication Critical patent/DE68928840D1/de
Publication of DE68928840T2 publication Critical patent/DE68928840T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/122—Tiling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Image Input (AREA)
  • Static Random-Access Memory (AREA)
  • Digital Computer Display Output (AREA)
  • Memory System (AREA)
  • Controls And Circuits For Display Device (AREA)
DE1989628840 1988-11-29 1989-11-29 Synchroner dynamischer Speicher Expired - Lifetime DE68928840T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/277,637 US5142637A (en) 1988-11-29 1988-11-29 Dynamic video RAM incorporating single clock random port control
US07/278,333 US5148523A (en) 1988-11-29 1988-11-29 Dynamic video RAM incorporationg on chip line modification
US07/277,687 US5148524A (en) 1988-11-29 1988-11-29 Dynamic video RAM incorporating on chip vector/image mode line modification

Publications (2)

Publication Number Publication Date
DE68928840D1 true DE68928840D1 (de) 1998-11-26
DE68928840T2 DE68928840T2 (de) 1999-04-01

Family

ID=27402922

Family Applications (9)

Application Number Title Priority Date Filing Date
DE1989629451 Expired - Lifetime DE68929451T2 (de) 1988-11-29 1989-11-29 Integrierte Schaltung mit synchronen Halbleiterspeicher, Methode zum Zugriff auf diesen Speicher und System mit einem solchen Speicher
DE1989629485 Expired - Lifetime DE68929485T2 (de) 1988-11-29 1989-11-29 Synchrone dynamische integrierte Speicherschaltung, Zugriffverfahren auf dieses System und System mit einem solchem Speicher
DE1989629407 Expired - Lifetime DE68929407T2 (de) 1988-11-29 1989-11-29 Integrierte Schaltung mit synchronem Halbleiter-Speicher, Methode zum Zugriff auf diesen Speicher und System mit einem solchen Speicher
DE1989629514 Expired - Lifetime DE68929514T2 (de) 1988-11-29 1989-11-29 Integrierter Schaltkreis mit synchronem Halbleiterspeicher, ein Verfahren zum Zugriff auf den besagten Speicher sowie ein System, das einen solchen Speicher beihaltet.
DE1989625569 Expired - Lifetime DE68925569T2 (de) 1988-11-29 1989-11-29 Dynamischer Video-RAM-Speicher
DE1989629195 Expired - Lifetime DE68929195T2 (de) 1988-11-29 1989-11-29 Integrierte Schaltung mit synchronem Speicher mit direktem Zugriff, Methode zum Zugriff auf diesen Speicher und System mit einem solchen Speicher
DE1989628840 Expired - Lifetime DE68928840T2 (de) 1988-11-29 1989-11-29 Synchroner dynamischer Speicher
DE1989628839 Expired - Lifetime DE68928839T2 (de) 1988-11-29 1989-11-29 System mit einem synchronen DRAM-Speicher
DE1989629482 Expired - Lifetime DE68929482T2 (de) 1988-11-29 1989-11-29 Integrierter Schaltkreis mit synchronem Halbleiterspeicher, ein Verfahren zum Zugriff auf den besagten Speicher sowie ein System, das einen solchen Speicher beinhaltet

Family Applications Before (6)

Application Number Title Priority Date Filing Date
DE1989629451 Expired - Lifetime DE68929451T2 (de) 1988-11-29 1989-11-29 Integrierte Schaltung mit synchronen Halbleiterspeicher, Methode zum Zugriff auf diesen Speicher und System mit einem solchen Speicher
DE1989629485 Expired - Lifetime DE68929485T2 (de) 1988-11-29 1989-11-29 Synchrone dynamische integrierte Speicherschaltung, Zugriffverfahren auf dieses System und System mit einem solchem Speicher
DE1989629407 Expired - Lifetime DE68929407T2 (de) 1988-11-29 1989-11-29 Integrierte Schaltung mit synchronem Halbleiter-Speicher, Methode zum Zugriff auf diesen Speicher und System mit einem solchen Speicher
DE1989629514 Expired - Lifetime DE68929514T2 (de) 1988-11-29 1989-11-29 Integrierter Schaltkreis mit synchronem Halbleiterspeicher, ein Verfahren zum Zugriff auf den besagten Speicher sowie ein System, das einen solchen Speicher beihaltet.
DE1989625569 Expired - Lifetime DE68925569T2 (de) 1988-11-29 1989-11-29 Dynamischer Video-RAM-Speicher
DE1989629195 Expired - Lifetime DE68929195T2 (de) 1988-11-29 1989-11-29 Integrierte Schaltung mit synchronem Speicher mit direktem Zugriff, Methode zum Zugriff auf diesen Speicher und System mit einem solchen Speicher

Family Applications After (2)

Application Number Title Priority Date Filing Date
DE1989628839 Expired - Lifetime DE68928839T2 (de) 1988-11-29 1989-11-29 System mit einem synchronen DRAM-Speicher
DE1989629482 Expired - Lifetime DE68929482T2 (de) 1988-11-29 1989-11-29 Integrierter Schaltkreis mit synchronem Halbleiterspeicher, ein Verfahren zum Zugriff auf den besagten Speicher sowie ein System, das einen solchen Speicher beinhaltet

Country Status (3)

Country Link
EP (9) EP0798733B1 (de)
JP (6) JP2557113B2 (de)
DE (9) DE68929451T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2740063B2 (ja) * 1990-10-15 1998-04-15 株式会社東芝 半導体記憶装置
US6249481B1 (en) 1991-10-15 2001-06-19 Kabushiki Kaisha Toshiba Semiconductor memory device
EP0487819B1 (de) * 1990-10-31 1997-03-05 International Business Machines Corporation Video-RAM mit schnellen Rücksetzung und Kopiermöglichkeit
NL194254C (nl) * 1992-02-18 2001-10-02 Evert Hans Van De Waal Jr Inrichting voor het converteren en/of integreren van beeldsignalen.
US6310821B1 (en) 1998-07-10 2001-10-30 Kabushiki Kaisha Toshiba Clock-synchronous semiconductor memory device and access method thereof
JP2774752B2 (ja) * 1992-03-19 1998-07-09 株式会社東芝 クロック同期型半導体記憶装置およびそのアクセス方法
DE69325119T2 (de) * 1992-03-19 1999-11-04 Kabushiki Kaisha Toshiba, Kawasaki Taktsynchronisierter Halbleiterspeicheranordnung und Zugriffsverfahren
JP2947664B2 (ja) * 1992-03-30 1999-09-13 株式会社東芝 画像専用半導体記憶装置
US6009234A (en) 1995-04-14 1999-12-28 Kabushiki Kaisha Toshiba Method of reproducing information
JP4236713B2 (ja) * 1997-07-30 2009-03-11 ソニー株式会社 記憶装置およびアクセス方法
JP4162348B2 (ja) * 2000-02-04 2008-10-08 株式会社東芝 メモリ混載画像処理用ｌｓｉおよび画像処理装置
KR100921683B1 (ko) * 2007-12-17 2009-10-15 한국전자통신연구원 키-값 데이터 모델을 위한 메모리 페이지 내 데이터저장방법
KR101226394B1 (ko) 2008-06-30 2013-01-24 후지쯔 세미컨덕터 가부시키가이샤 메모리 장치
US8074040B2 (en) * 2008-09-23 2011-12-06 Mediatek Inc. Flash device and method for improving performance of flash device
KR20160132243A (ko) * 2015-05-08 2016-11-17 에스케이하이닉스 주식회사 반도체 메모리 장치

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50102236A (de) * 1974-01-07 1975-08-13
US3996559A (en) * 1974-11-07 1976-12-07 International Business Machines Corporation Method and apparatus for accessing horizontal sequences, vertical sequences and regularly spaced rectangular subarrays from an array stored in a modified word organized random access memory system
DE3015125A1 (de) * 1980-04-19 1981-10-22 Ibm Deutschland Gmbh, 7000 Stuttgart Einrichtung zur speicherung und darstellung graphischer information
US4546451A (en) * 1982-02-12 1985-10-08 Metheus Corporation Raster graphics display refresh memory architecture offering rapid access speed
WO1984003970A1 (en) * 1983-03-30 1984-10-11 Siemens Ag Hybrid associative memory and method for the retrieval and sorting of data contained therein
JPS60113396A (ja) * 1983-11-25 1985-06-19 Toshiba Corp メモリｌｓｉ
US4663735A (en) * 1983-12-30 1987-05-05 Texas Instruments Incorporated Random/serial access mode selection circuit for a video memory system
JPS6198441A (ja) * 1984-10-19 1986-05-16 Fujitsu Ltd 半導体集積回路
US4712190A (en) * 1985-01-25 1987-12-08 Digital Equipment Corporation Self-timed random access memory chip
US4755810A (en) * 1985-04-05 1988-07-05 Tektronix, Inc. Frame buffer memory
JPH0816882B2 (ja) * 1985-06-17 1996-02-21 株式会社日立製作所 半導体記憶装置
JP2575090B2 (ja) * 1985-06-17 1997-01-22 株式会社日立製作所 半導体記憶装置
JPS62223891A (ja) * 1986-03-26 1987-10-01 Hitachi Ltd 半導体記憶装置
JPS6334795A (ja) * 1986-07-29 1988-02-15 Mitsubishi Electric Corp 半導体記憶装置
DE3628286A1 (de) * 1986-08-20 1988-02-25 Staerk Juergen Dipl Ing Dipl I Prozessor mit integriertem speicher
US4870619A (en) * 1986-10-14 1989-09-26 Monolithic Systems Corp. Memory chip array with inverting and non-inverting address drivers
JPS63123142A (ja) * 1986-11-12 1988-05-26 Nec Corp 半導体記憶装置
US5226147A (en) * 1987-11-06 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device for simple cache system
JP2593322B2 (ja) * 1987-11-06 1997-03-26 三菱電機株式会社 半導体記憶装置
JP3992757B2 (ja) * 1991-04-23 2007-10-17 テキサス インスツルメンツ インコーポレイテツド マイクロプロセッサと同期するメモリ、及びデータプロセッサ、同期メモリ、周辺装置とシステムクロックを含むシステム

Also Published As

Publication number Publication date
DE68929514T2 (de) 2004-12-30
EP0635817A3 (de) 1995-05-17
EP0635817B1 (de) 1998-10-21
EP0778576A3 (de) 1998-03-18
DE68929195D1 (de) 2000-05-18
DE68925569D1 (de) 1996-03-14
DE68929514D1 (de) 2004-03-25
EP0635816A2 (de) 1995-01-25
DE68929485T2 (de) 2004-07-29
JP2557113B2 (ja) 1996-11-27
JPH07325752A (ja) 1995-12-12
EP0778577A2 (de) 1997-06-11
EP0778577A3 (de) 1998-02-18
JPH02250132A (ja) 1990-10-05
EP0798734A3 (de) 1998-02-18
DE68929451D1 (de) 2003-02-20
EP0798733A3 (de) 1998-02-18
EP0778576A2 (de) 1997-06-11
EP0778579A3 (de) 1998-02-18
JP2642899B2 (ja) 1997-08-20
EP0778579A2 (de) 1997-06-11
DE68928840T2 (de) 1999-04-01
JPH07287978A (ja) 1995-10-31
JPH07271970A (ja) 1995-10-20
JP2593060B2 (ja) 1997-03-19
EP0635817A2 (de) 1995-01-25
EP0778576B1 (de) 2000-04-12
DE68928839T2 (de) 1999-04-01
EP0371488A3 (de) 1992-08-12
EP0798734A2 (de) 1997-10-01
EP0778577B1 (de) 2002-06-12
DE68929195T2 (de) 2000-12-21
EP0778578A3 (de) 1998-02-18
EP0798734B1 (de) 2004-02-18
EP0635816B1 (de) 1998-10-21
EP0778578B1 (de) 2003-01-15
DE68929482T2 (de) 2004-06-24
DE68925569T2 (de) 1996-08-08
EP0798733A2 (de) 1997-10-01
DE68929407T2 (de) 2003-01-16
DE68929451T2 (de) 2003-06-05
JPH07271657A (ja) 1995-10-20
EP0371488B1 (de) 1996-01-31
EP0635816A3 (de) 1995-05-17
EP0778578A2 (de) 1997-06-11
EP0798733B1 (de) 2003-08-13
JPH087565A (ja) 1996-01-12
DE68929485D1 (de) 2003-11-06
DE68929407D1 (de) 2002-07-18
EP0371488A2 (de) 1990-06-06
DE68929482D1 (de) 2003-09-18
EP0778579B1 (de) 2003-10-01
DE68928839D1 (de) 1998-11-26
JP2604568B2 (ja) 1997-04-30
JP2940809B2 (ja) 1999-08-25

Similar Documents

Publication Publication Date Title
DE3876415D1 (de) Dynamischer direktzugriffsspeicher.
KR890012387A (ko) 반도체 기억장치
DE3771288D1 (de) Dynamischer speicher mit wahlfreiem zugriff.
DE69129016D1 (de) Synchroner halbleiterspeicher
DE69117001D1 (de) Synchroner dynamischer Direktzugriffspeicher
NL193295B (nl) Dynamische halfgeleidergeheugeneenheid.
DE3584694D1 (de) Dynamischer direktzugriffspeicher.
DE69121483D1 (de) Dynamische Halbleiterspeicherzelle
DE69536100D1 (de) Dynamischer Speicher
DK331889D0 (da) Vindmoelle
DE3782756D1 (de) Direktzugriffspeichereinrichtung.
KR880013252A (ko) 반도체 기억장치
DE69316955D1 (de) Rechenanlage mit synchronem, dynamischem Speicher
KR890016569A (ko) 반도체 기억장치
KR900011010A (ko) 반도체 기억장치
DE68928840D1 (de) Synchroner dynamischer Speicher
DE69330819D1 (de) Synchrone LSI-Speicheranordnung
KR890015210A (ko) 복합메모리매체
KR900008521A (ko) 반도체 기억장치
DE3783100D1 (de) Festwertspeicheranordnung.
KR900006986A (ko) 반도체메모리
DE69024945D1 (de) Halbleiterspeicheranordnung
DE69027474D1 (de) Statischer Speicher
DE69025284D1 (de) Halbleiterspeicher dynamischen Typs
DE69521656D1 (de) Dynamischer Speicher

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP