DE68922073D1 - Elektronisches System mit einem Mikroprozessor und Koprozessor, die auf einer Schaltplatte montiert sind. - Google Patents

Elektronisches System mit einem Mikroprozessor und Koprozessor, die auf einer Schaltplatte montiert sind.

Info

Publication number
DE68922073D1
DE68922073D1 DE68922073T DE68922073T DE68922073D1 DE 68922073 D1 DE68922073 D1 DE 68922073D1 DE 68922073 T DE68922073 T DE 68922073T DE 68922073 T DE68922073 T DE 68922073T DE 68922073 D1 DE68922073 D1 DE 68922073D1
Authority
DE
Germany
Prior art keywords
coprocessor
microprocessor
circuit board
electronic system
electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68922073T
Other languages
English (en)
Other versions
DE68922073T2 (de
Inventor
Tatsuo Okahashi
Atsushi Hasegawa
Masao Naito
Norio Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Microcomputer System Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63300780A external-priority patent/JPH02148860A/ja
Priority claimed from JP63308522A external-priority patent/JP2856324B2/ja
Application filed by Hitachi Microcomputer System Ltd, Hitachi Ltd filed Critical Hitachi Microcomputer System Ltd
Publication of DE68922073D1 publication Critical patent/DE68922073D1/de
Application granted granted Critical
Publication of DE68922073T2 publication Critical patent/DE68922073T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Multi Processors (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Combinations Of Printed Boards (AREA)
DE68922073T 1988-11-30 1989-11-23 Elektronisches System mit einem Mikroprozessor und Koprozessor, die auf einer Schaltplatte montiert sind. Expired - Fee Related DE68922073T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63300780A JPH02148860A (ja) 1988-11-30 1988-11-30 半導体装置
JP63308522A JP2856324B2 (ja) 1988-12-05 1988-12-05 電子装置

Publications (2)

Publication Number Publication Date
DE68922073D1 true DE68922073D1 (de) 1995-05-11
DE68922073T2 DE68922073T2 (de) 1995-08-10

Family

ID=26562457

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68922073T Expired - Fee Related DE68922073T2 (de) 1988-11-30 1989-11-23 Elektronisches System mit einem Mikroprozessor und Koprozessor, die auf einer Schaltplatte montiert sind.

Country Status (3)

Country Link
US (1) US4994902A (de)
EP (2) EP0602338A1 (de)
DE (1) DE68922073T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2748562B2 (ja) * 1988-07-13 1998-05-06 セイコーエプソン株式会社 画像処理装置
US5293072A (en) * 1990-06-25 1994-03-08 Fujitsu Limited Semiconductor device having spherical terminals attached to the lead frame embedded within the package body
US5287247A (en) * 1990-09-21 1994-02-15 Lsi Logic Corporation Computer system module assembly
JP2876773B2 (ja) * 1990-10-22 1999-03-31 セイコーエプソン株式会社 プログラム命令語長可変型計算装置及びデータ処理装置
US5929517A (en) 1994-12-29 1999-07-27 Tessera, Inc. Compliant integrated circuit package and method of fabricating the same
JP3412942B2 (ja) * 1995-01-11 2003-06-03 株式会社東芝 半導体装置
JP3362545B2 (ja) * 1995-03-09 2003-01-07 ソニー株式会社 半導体装置の製造方法
US5777383A (en) * 1996-05-09 1998-07-07 Lsi Logic Corporation Semiconductor chip package with interconnect layers and routing and testing methods
JP3177464B2 (ja) * 1996-12-12 2001-06-18 株式会社日立製作所 入出力回路セル及び半導体集積回路装置
US6198688B1 (en) * 1998-04-02 2001-03-06 Hyundai Electronics Industries, Co., Ltd. Interface for synchronous semiconductor memories
US6049136A (en) * 1998-06-03 2000-04-11 Hewlett-Packard Company Integrated circuit having unique lead configuration
DE19904363B4 (de) * 1999-02-03 2007-10-04 Siemens Ag Schaltungsanordnung zum Entstören von integrierten Schaltkreisen
US6885106B1 (en) 2001-01-11 2005-04-26 Tessera, Inc. Stacked microelectronic assemblies and methods of making same
GB2377080B (en) * 2001-09-11 2003-05-07 Sendo Int Ltd Integrated circuit package and printed circuit board arrangement
WO2003032370A2 (en) * 2001-10-09 2003-04-17 Tessera, Inc. Stacked packages
US7335995B2 (en) * 2001-10-09 2008-02-26 Tessera, Inc. Microelectronic assembly having array including passive elements and interconnects
US6977440B2 (en) * 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
US7073048B2 (en) * 2002-02-04 2006-07-04 Silicon Lease, L.L.C. Cascaded microcomputer array and method
US6765288B2 (en) * 2002-08-05 2004-07-20 Tessera, Inc. Microelectronic adaptors, assemblies and methods
US7053485B2 (en) * 2002-08-16 2006-05-30 Tessera, Inc. Microelectronic packages with self-aligning features
US7294928B2 (en) * 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
US7071547B2 (en) * 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
JP2005123362A (ja) * 2003-10-16 2005-05-12 Hitachi Ltd 接続用取付基板及びディスクアレイ制御装置の接続用取付基板
US7061121B2 (en) 2003-11-12 2006-06-13 Tessera, Inc. Stacked microelectronic assemblies with central contacts
TWI236122B (en) * 2004-02-27 2005-07-11 Via Tech Inc A low thermal expansion build-up layer packaging and a method to package a die using the same
US7545029B2 (en) * 2006-08-18 2009-06-09 Tessera, Inc. Stack microelectronic assemblies
USD719537S1 (en) * 2013-05-08 2014-12-16 Mitsubishi Electric Corporation Semiconductor device
US9955605B2 (en) * 2016-03-30 2018-04-24 Intel Corporation Hardware interface with space-efficient cell pattern

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2040499A (en) * 1979-01-08 1980-08-28 Notley P J Methods of Manufacturing Electrical-circuit Layouts and Items for Use Therein
DE3210998A1 (de) * 1982-03-25 1983-10-06 Hartmann Karlheinz Elektronic Leiterplatte
US4551746A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation
US4513355A (en) * 1983-06-15 1985-04-23 Motorola, Inc. Metallization and bonding means and method for VLSI packages
US4847732A (en) * 1983-09-15 1989-07-11 Mosaic Systems, Inc. Wafer and method of making same
US4631572A (en) * 1983-09-27 1986-12-23 Trw Inc. Multiple path signal distribution to large scale integration chips
DE3539040A1 (de) * 1985-11-04 1987-05-07 Telefonbau & Normalzeit Gmbh Leiterbahnanordnung und schaltungsanordnung fuer mit integrierten schaltkreisen bestueckte leiterplatten
DE3542208A1 (de) * 1985-11-29 1987-06-04 Diehl Gmbh & Co Leiterbahnen-anordnung
KR900008995B1 (ko) * 1986-12-19 1990-12-17 페어차일드 세미콘덕터 코포레이션 고주파 반도체 소자용 세라믹 패키지
IT211826Z2 (it) * 1987-09-15 1989-05-25 Microset Srl Scheda madre a circuito stampato per bus di microprocessori.
US4784970A (en) * 1987-11-18 1988-11-15 Grumman Aerospace Corporation Process for making a double wafer moated signal processor
US4794092A (en) * 1987-11-18 1988-12-27 Grumman Aerospace Corporation Single wafer moated process

Also Published As

Publication number Publication date
EP0371696A2 (de) 1990-06-06
DE68922073T2 (de) 1995-08-10
EP0371696B1 (de) 1995-04-05
US4994902A (en) 1991-02-19
EP0371696A3 (de) 1991-07-24
EP0602338A1 (de) 1994-06-22

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee