DE69020204D1 - Mehrschichtige gedruckte Leiterplatte. - Google Patents

Mehrschichtige gedruckte Leiterplatte.

Info

Publication number
DE69020204D1
DE69020204D1 DE69020204T DE69020204T DE69020204D1 DE 69020204 D1 DE69020204 D1 DE 69020204D1 DE 69020204 T DE69020204 T DE 69020204T DE 69020204 T DE69020204 T DE 69020204T DE 69020204 D1 DE69020204 D1 DE 69020204D1
Authority
DE
Germany
Prior art keywords
circuit board
printed circuit
layer printed
layer
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69020204T
Other languages
English (en)
Other versions
DE69020204T2 (de
Inventor
Michael Scott Dampier
Ronald Jay Prilik
Norman Richard Rapoport
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69020204D1 publication Critical patent/DE69020204D1/de
Publication of DE69020204T2 publication Critical patent/DE69020204T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
DE69020204T 1989-03-29 1990-03-14 Mehrschichtige gedruckte Leiterplatte. Expired - Fee Related DE69020204T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/330,293 US4928061A (en) 1989-03-29 1989-03-29 Multi-layer printed circuit board

Publications (2)

Publication Number Publication Date
DE69020204D1 true DE69020204D1 (de) 1995-07-27
DE69020204T2 DE69020204T2 (de) 1996-02-15

Family

ID=23289119

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69020204T Expired - Fee Related DE69020204T2 (de) 1989-03-29 1990-03-14 Mehrschichtige gedruckte Leiterplatte.

Country Status (4)

Country Link
US (1) US4928061A (de)
EP (1) EP0389865B1 (de)
JP (1) JPH0724336B2 (de)
DE (1) DE69020204T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101149A (en) * 1989-07-18 1992-03-31 National Semiconductor Corporation Modifiable IC board
US5148103A (en) * 1990-10-31 1992-09-15 Hughes Aircraft Company Apparatus for testing integrated circuits
US5144228A (en) * 1991-04-23 1992-09-01 International Business Machines Corporation Probe interface assembly
US5216361A (en) * 1991-07-10 1993-06-01 Schlumberger Technologies, Inc. Modular board test system having wireless receiver
US5323105A (en) * 1991-08-08 1994-06-21 International Business Machines Corporation Test template for monitoring the pins of a multi-pin chip cirucit package
US5307012A (en) * 1991-12-03 1994-04-26 Intel Corporation Test substation for testing semi-conductor packages
JP3338527B2 (ja) * 1992-10-07 2002-10-28 富士通株式会社 高密度積層形のコネクタ、及び、コネクタの設計方法
US5489852A (en) * 1992-11-06 1996-02-06 Advanced Micro Devices, Inc. System for interfacing wafer sort prober apparatus and packaged IC handler apparatus to a common test computer
US5381306A (en) * 1993-08-20 1995-01-10 Convex Computer Corporation Method and apparatus for delivering power using a multiplane power via matrix
US20030199179A1 (en) * 1993-11-16 2003-10-23 Formfactor, Inc. Contact tip structure for microelectronic interconnection elements and method of making same
US20020053734A1 (en) 1993-11-16 2002-05-09 Formfactor, Inc. Probe card assembly and kit, and methods of making same
EP0707214A3 (de) * 1994-10-14 1997-04-16 Hughes Aircraft Co Multiport-Membranfühler zum Testen vollständiger Wafer
US5642054A (en) * 1995-08-08 1997-06-24 Hughes Aircraft Company Active circuit multi-port membrane probe for full wafer testing
US5705932A (en) * 1995-10-10 1998-01-06 Xilinx, Inc. System for expanding space provided by test computer to test multiple integrated circuits simultaneously
US5945837A (en) * 1995-10-10 1999-08-31 Xilinx, Inc. Interface structure for an integrated circuit device tester
US6118286A (en) * 1995-10-10 2000-09-12 Xilinx, Inc. Semiconductor device tester-to-handler Interface board with large test area
US8033838B2 (en) 1996-02-21 2011-10-11 Formfactor, Inc. Microelectronic contact structure
US6085962A (en) * 1997-09-08 2000-07-11 Micron Technology, Inc. Wire bond monitoring system for layered packages
US7102367B2 (en) * 2002-07-23 2006-09-05 Fujitsu Limited Probe card and testing method of semiconductor chip, capacitor and manufacturing method thereof
DE102018132098A1 (de) * 2018-12-13 2020-06-18 Thyssenkrupp Ag Elektronische Leiterplatte

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2816273A (en) * 1952-08-01 1957-12-10 Sprague Electric Co Artificial transmission line
US4183074A (en) * 1977-04-16 1980-01-08 Wallace Clarence L Manufacture of multi-layered electrical assemblies
DE2830757C2 (de) * 1978-07-13 1987-01-22 MWB Messwandler-Bau AG, 8600 Bamberg Transformatorwicklung und Verfahren zu ihrer Herstellung
US4288841A (en) * 1979-09-20 1981-09-08 Bell Telephone Laboratories, Incorporated Double cavity semiconductor chip carrier
JPS57159051A (en) * 1981-03-27 1982-10-01 Hitachi Ltd Semiconductor device
JPS5851436U (ja) * 1981-10-01 1983-04-07 日本電気株式会社 可変容量形積層セラミツクコンデンサ
JPS58133952U (ja) * 1982-03-03 1983-09-09 ミツミ電機株式会社 基板構造
US4543715A (en) * 1983-02-28 1985-10-01 Allied Corporation Method of forming vertical traces on printed circuit board
US4628411A (en) * 1984-03-12 1986-12-09 International Business Machines Corporation Apparatus for directly powering a multi-chip module from a power distribution bus
JPS6181131U (de) * 1984-11-02 1986-05-29
JPH023631Y2 (de) * 1984-12-28 1990-01-29
US4628406A (en) * 1985-05-20 1986-12-09 Tektronix, Inc. Method of packaging integrated circuit chips, and integrated circuit package
JPS6331520U (de) * 1986-08-15 1988-03-01
US4734825A (en) * 1986-09-05 1988-03-29 Motorola Inc. Integrated circuit stackable package
JPH067138B2 (ja) * 1986-10-27 1994-01-26 東京エレクトロン株式会社 プローブ装置
JPS63193877U (de) * 1987-06-02 1988-12-14

Also Published As

Publication number Publication date
DE69020204T2 (de) 1996-02-15
EP0389865A3 (de) 1992-01-22
US4928061A (en) 1990-05-22
JPH02281794A (ja) 1990-11-19
EP0389865A2 (de) 1990-10-03
JPH0724336B2 (ja) 1995-03-15
EP0389865B1 (de) 1995-06-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee