DE60235267D1 - Herstellungsverfahren einer dreidimensionalen vorrichtung - Google Patents

Herstellungsverfahren einer dreidimensionalen vorrichtung

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Publication number
DE60235267D1
DE60235267D1 DE60235267T DE60235267T DE60235267D1 DE 60235267 D1 DE60235267 D1 DE 60235267D1 DE 60235267 T DE60235267 T DE 60235267T DE 60235267 T DE60235267 T DE 60235267T DE 60235267 D1 DE60235267 D1 DE 60235267D1
Authority
DE
Germany
Prior art keywords
wafers
vias
studs
openings
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60235267T
Other languages
English (en)
Inventor
Bernhard H Pogge
Roy Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
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Publication of DE60235267D1 publication Critical patent/DE60235267D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
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    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
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    • H01L2924/14Integrated circuits
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
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JP4575782B2 (ja) 2010-11-04
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EP1573799A1 (de) 2005-09-14
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