DE60211822T2 - Verfahren und Vorrichtung zur Synchronisierung eines mehrstufigen Multiplexers - Google Patents
Verfahren und Vorrichtung zur Synchronisierung eines mehrstufigen Multiplexers Download PDFInfo
- Publication number
- DE60211822T2 DE60211822T2 DE60211822T DE60211822T DE60211822T2 DE 60211822 T2 DE60211822 T2 DE 60211822T2 DE 60211822 T DE60211822 T DE 60211822T DE 60211822 T DE60211822 T DE 60211822T DE 60211822 T2 DE60211822 T2 DE 60211822T2
- Authority
- DE
- Germany
- Prior art keywords
- multiplexer
- test pattern
- stage
- output
- controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 28
- 238000012360 testing method Methods 0.000 claims description 101
- 230000001360 synchronised effect Effects 0.000 claims description 38
- 230000003595 spectral effect Effects 0.000 claims description 21
- 230000008859 change Effects 0.000 claims description 5
- 238000013507 mapping Methods 0.000 claims 2
- 238000001914 filtration Methods 0.000 claims 1
- 238000012937 correction Methods 0.000 description 25
- 238000010586 diagram Methods 0.000 description 21
- 230000003068 static effect Effects 0.000 description 15
- 239000013598 vector Substances 0.000 description 10
- 230000003111 delayed effect Effects 0.000 description 8
- 238000013459 approach Methods 0.000 description 5
- 238000012805 post-processing Methods 0.000 description 4
- 230000001934 delay Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/04—Distributors combined with modulators or demodulators
- H04J3/047—Distributors with transistors or integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Tests Of Electronic Circuits (AREA)
- Time-Division Multiplex Systems (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/967,390 US7106227B2 (en) | 2001-09-28 | 2001-09-28 | Method and apparatus for synchronizing a multiple-stage multiplexer |
| US967390 | 2001-09-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE60211822D1 DE60211822D1 (de) | 2006-07-06 |
| DE60211822T2 true DE60211822T2 (de) | 2007-05-16 |
Family
ID=25512723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60211822T Expired - Fee Related DE60211822T2 (de) | 2001-09-28 | 2002-07-25 | Verfahren und Vorrichtung zur Synchronisierung eines mehrstufigen Multiplexers |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7106227B2 (enExample) |
| EP (1) | EP1298823B1 (enExample) |
| JP (1) | JP2003124903A (enExample) |
| DE (1) | DE60211822T2 (enExample) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7020210B2 (en) * | 2001-10-23 | 2006-03-28 | Broadcom Corporation | Inter-device adaptable interfacing clock skewing |
| US7672301B2 (en) * | 2002-05-02 | 2010-03-02 | Ciena Corporation | Distribution stage for enabling efficient expansion of a switching network |
| US7319706B2 (en) * | 2002-08-12 | 2008-01-15 | Broadcom Corporation | Symmetrical clock distribution in multi-stage high speed data conversion circuits |
| US7443890B2 (en) * | 2002-08-12 | 2008-10-28 | Broadcom Corporation | Multi-stage multiplexing chip set having switchable forward/reverse clock relationship |
| US7266133B2 (en) * | 2002-11-13 | 2007-09-04 | General Instrument Corporation | Methods and apparatus for statistical multiplexing with distributed multiplexers |
| US7342977B2 (en) * | 2002-11-26 | 2008-03-11 | Lsi Logic Corporation | Serial data transmitter with bit doubling |
| US7471752B2 (en) * | 2004-08-06 | 2008-12-30 | Lattice Semiconductor Corporation | Data transmission synchronization |
| US7848318B2 (en) | 2005-08-03 | 2010-12-07 | Altera Corporation | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits |
| US7245240B1 (en) * | 2006-03-07 | 2007-07-17 | Altera Corporation | Integrated circuit serializers with two-phase global master clocks |
| US8417810B2 (en) * | 2007-01-10 | 2013-04-09 | Broadcom Corporation | System and method for managing counters |
| TW200835151A (en) * | 2007-02-15 | 2008-08-16 | Univ Nat Chiao Tung | Low-power dynamic sequential controlling multiplexer |
| US8989214B2 (en) | 2007-12-17 | 2015-03-24 | Altera Corporation | High-speed serial data signal receiver circuitry |
| US7948975B2 (en) * | 2008-03-03 | 2011-05-24 | IPLight Ltd. | Transparent switching fabric for multi-gigabit transport |
| TWI449342B (zh) * | 2012-01-20 | 2014-08-11 | Silicon Motion Inc | 串化器及資料串化方法 |
| US9246616B2 (en) * | 2014-02-06 | 2016-01-26 | Cisco Technologies, Inc. | Clock phase compensator for multi-stage time division multiplexer |
| US10110334B2 (en) * | 2016-04-25 | 2018-10-23 | Macom Connectivity Solutions, Llc | High speed serializer using quadrature clocks |
| US10340904B2 (en) * | 2016-06-28 | 2019-07-02 | Altera Corporation | Method and apparatus for phase-aligned 2X frequency clock generation |
| US10193556B2 (en) * | 2016-11-11 | 2019-01-29 | Skyworks Solutions, Inc. | Method and apparatus for configurable control of an electronic device |
| WO2021201247A1 (ja) * | 2020-04-03 | 2021-10-07 | 凸版印刷株式会社 | 信号検出回路、駆動検出回路、センサアレイおよびセンサシステム |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2811851C2 (de) * | 1978-03-17 | 1980-03-27 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Rahmensynchronisierung eines Zeitmultiplexsystems |
| JPH02165744A (ja) * | 1988-12-20 | 1990-06-26 | Toshiba Corp | データ時分割処理装置 |
| DE69029122T2 (de) * | 1989-06-16 | 1997-04-03 | Advantest Corp | Prüfmustergenerator |
| JPH03201735A (ja) | 1989-12-28 | 1991-09-03 | Advantest Corp | データ多重化装置 |
| US5157277A (en) | 1990-12-28 | 1992-10-20 | Compaq Computer Corporation | Clock buffer with adjustable delay and fixed duty cycle output |
| US5182467A (en) * | 1991-08-22 | 1993-01-26 | Triquint Semiconductor, Inc. | High performance multiplexer for improving bit error rate |
| JP3233773B2 (ja) * | 1994-03-18 | 2001-11-26 | 富士通株式会社 | 試験回路、自己試験方法及び通常試験方法 |
| JPH0832425A (ja) * | 1994-07-18 | 1996-02-02 | Fujitsu Ltd | データ読み取りタイミング可変回路 |
| JPH0955667A (ja) * | 1995-08-10 | 1997-02-25 | Mitsubishi Electric Corp | マルチプレクサ，及びデマルチプレクサ |
| US5969655A (en) * | 1995-12-15 | 1999-10-19 | Matsushida Electric Industrial Co., Ltd. | Digital convergence correction device outputting an analog correction signal |
| US5856753A (en) * | 1996-03-29 | 1999-01-05 | Cypress Semiconductor Corp. | Output circuit for 3V/5V clock chip duty cycle adjustments |
| US6026076A (en) * | 1997-08-29 | 2000-02-15 | Lucent Technologies Inc. | Detecting digital multiplexer faults |
| US6201829B1 (en) * | 1998-04-03 | 2001-03-13 | Adaptec, Inc. | Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator |
| JP2000013347A (ja) * | 1998-06-19 | 2000-01-14 | Nec Eng Ltd | 多重化回路及びその多重化のための並直列変換用ラッチクロック生成回路 |
| US6442085B1 (en) * | 2000-10-02 | 2002-08-27 | International Business Machines Corporation | Self-Test pattern to detect stuck open faults |
| US6961317B2 (en) * | 2001-09-28 | 2005-11-01 | Agilent Technologies, Inc. | Identifying and synchronizing permuted channels in a parallel channel bit error rate tester |
-
2001
- 2001-09-28 US US09/967,390 patent/US7106227B2/en not_active Expired - Fee Related
-
2002
- 2002-07-25 EP EP02016662A patent/EP1298823B1/en not_active Expired - Lifetime
- 2002-07-25 DE DE60211822T patent/DE60211822T2/de not_active Expired - Fee Related
- 2002-09-27 JP JP2002282218A patent/JP2003124903A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP1298823B1 (en) | 2006-05-31 |
| US20030063626A1 (en) | 2003-04-03 |
| JP2003124903A (ja) | 2003-04-25 |
| DE60211822D1 (de) | 2006-07-06 |
| US7106227B2 (en) | 2006-09-12 |
| EP1298823A3 (en) | 2005-05-04 |
| EP1298823A2 (en) | 2003-04-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D. STAATES, US |
|
| 8339 | Ceased/non-payment of the annual fee |