DE602004016655D1 - Verfahren und vorrichtung zum teilweisen auffrischen von drams - Google Patents

Verfahren und vorrichtung zum teilweisen auffrischen von drams

Info

Publication number
DE602004016655D1
DE602004016655D1 DE602004016655T DE602004016655T DE602004016655D1 DE 602004016655 D1 DE602004016655 D1 DE 602004016655D1 DE 602004016655 T DE602004016655 T DE 602004016655T DE 602004016655 T DE602004016655 T DE 602004016655T DE 602004016655 D1 DE602004016655 D1 DE 602004016655D1
Authority
DE
Germany
Prior art keywords
refreshing drams
partially refreshing
partially
drams
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004016655T
Other languages
English (en)
Inventor
Jun Shi
Animesh Mishra
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE602004016655D1 publication Critical patent/DE602004016655D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622—Partial refresh of memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4065—Low level details of refresh operations
DE602004016655T 2003-07-01 2004-06-30 Verfahren und vorrichtung zum teilweisen auffrischen von drams Active DE602004016655D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/612,585 US6876593B2 (en) 2003-07-01 2003-07-01 Method and apparatus for partial refreshing of DRAMS
PCT/US2004/021216 WO2005006341A1 (en) 2003-07-01 2004-06-30 Method and apparatus for partial refreshing of drams

Publications (1)

Publication Number Publication Date
DE602004016655D1 true DE602004016655D1 (de) 2008-10-30

Family

ID=33552540

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004016655T Active DE602004016655D1 (de) 2003-07-01 2004-06-30 Verfahren und vorrichtung zum teilweisen auffrischen von drams

Country Status (8)

Country Link
US (1) US6876593B2 (de)
EP (1) EP1639604B1 (de)
JP (1) JP2007527592A (de)
KR (1) KR20060029272A (de)
CN (1) CN1839446B (de)
AT (1) ATE408882T1 (de)
DE (1) DE602004016655D1 (de)
WO (1) WO2005006341A1 (de)

Families Citing this family (29)

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US9087603B2 (en) * 2003-09-30 2015-07-21 Intel Corporation Method and apparatus for selective DRAM precharge
US7345940B2 (en) * 2003-11-18 2008-03-18 Infineon Technologies Ag Method and circuit configuration for refreshing data in a semiconductor memory
US7099234B2 (en) * 2004-06-28 2006-08-29 United Memories, Inc. Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM
US7145823B2 (en) * 2004-06-30 2006-12-05 Intel Corporation Method and apparatus to implement a temperature control mechanism on a memory device
US7342841B2 (en) * 2004-12-21 2008-03-11 Intel Corporation Method, apparatus, and system for active refresh management
KR100642759B1 (ko) * 2005-01-28 2006-11-10 삼성전자주식회사 선택적 리프레쉬가 가능한 반도체 메모리 디바이스
US7616508B1 (en) * 2006-08-10 2009-11-10 Actel Corporation Flash-based FPGA with secure reprogramming
US7515494B2 (en) * 2006-11-14 2009-04-07 Promos Technologies Pte.Ltd Refresh period adjustment technique for dynamic random access memories (DRAM) and integrated circuit devices incorporating embedded DRAM
US20080258909A1 (en) * 2007-04-18 2008-10-23 Brian Nedward Meyer Methods and systems for automated data management
US7590021B2 (en) * 2007-07-26 2009-09-15 Qualcomm Incorporated System and method to reduce dynamic RAM power consumption via the use of valid data indicators
US8725520B2 (en) * 2007-09-07 2014-05-13 Qualcomm Incorporated Power efficient batch-frame audio decoding apparatus, system and method
US7962695B2 (en) * 2007-12-04 2011-06-14 International Business Machines Corporation Method and system for integrating SRAM and DRAM architecture in set associative cache
US20090144507A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US20090144504A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US7882302B2 (en) * 2007-12-04 2011-02-01 International Business Machines Corporation Method and system for implementing prioritized refresh of DRAM based cache
US8024513B2 (en) * 2007-12-04 2011-09-20 International Business Machines Corporation Method and system for implementing dynamic refresh protocols for DRAM based cache
US8108609B2 (en) * 2007-12-04 2012-01-31 International Business Machines Corporation Structure for implementing dynamic refresh protocols for DRAM based cache
US8392650B2 (en) * 2010-04-01 2013-03-05 Intel Corporation Fast exit from self-refresh state of a memory device
US8356155B2 (en) * 2010-09-13 2013-01-15 Advanced Micro Devices, Inc. Dynamic RAM Phy interface with configurable power states
KR20150006467A (ko) * 2012-06-07 2015-01-16 후지쯔 가부시끼가이샤 선택적으로 메모리의 리프레시를 행하는 제어 장치
KR101974108B1 (ko) * 2012-07-30 2019-08-23 삼성전자주식회사 리프레쉬 어드레스 생성기, 이를 포함하는 휘발성 메모리 장치 및 휘발성 메모리 장치의 리프레쉬 방법
KR101436442B1 (ko) * 2013-01-03 2014-09-01 고려대학교 산학협력단 읽기 및 쓰기 접근에 따른 선택적 리프레쉬 기능을 구비한 동적 메모리 장치 및 그 선택적 리프레쉬 방법
US9355689B2 (en) * 2013-08-20 2016-05-31 Oracle International Corporation Detection of multiple accesses to a row address of a dynamic memory within a refresh period
US10484519B2 (en) 2014-12-01 2019-11-19 Hewlett Packard Enterprise Development Lp Auto-negotiation over extended backplane
WO2017065732A1 (en) 2015-10-12 2017-04-20 Hewlett Packard Enterprise Development Lp Switch network architecture
US20180293189A1 (en) * 2015-10-13 2018-10-11 Hewlett Packard Enterprise Development Lp Memory manager for autonomous memory device
KR102373544B1 (ko) 2015-11-06 2022-03-11 삼성전자주식회사 요청 기반의 리프레쉬를 수행하는 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법
US10559374B2 (en) * 2017-02-20 2020-02-11 Piecemakers Technology, Inc. Circuit topology of memory chips with embedded function test pattern generation module connected to normal access port physical layer
US20190066760A1 (en) * 2017-08-23 2019-02-28 Nanya Technology Corporation Dram and method for operating the same

Family Cites Families (8)

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Publication number Priority date Publication date Assignee Title
US5041964A (en) * 1989-06-12 1991-08-20 Grid Systems Corporation Low-power, standby mode computer
JP4246812B2 (ja) * 1997-06-12 2009-04-02 パナソニック株式会社 半導体回路及びその制御方法
JPH1166843A (ja) * 1997-08-08 1999-03-09 Mitsubishi Electric Corp 半導体記憶装置
JP2000021162A (ja) * 1998-07-03 2000-01-21 Mitsubishi Electric Corp 揮発性メモリおよびエンベッデッド・ダイナミック・ランダム・アクセス・メモリ
JP2004288226A (ja) * 2001-03-30 2004-10-14 Internatl Business Mach Corp <Ibm> Ｄｒａｍ及びｄｒａｍのリフレッシュ方法
JP2002373489A (ja) * 2001-06-15 2002-12-26 Mitsubishi Electric Corp 半導体記憶装置
TW514920B (en) * 2001-07-20 2002-12-21 United Microelectronics Corp Selective memory refreshing circuit and refreshing method
JP4459495B2 (ja) * 2001-12-13 2010-04-28 富士通マイクロエレクトロニクス株式会社 半導体記憶装置のリフレッシュ制御方法、及び該制御方法を有する半導体記憶装置

Also Published As

Publication number Publication date
EP1639604B1 (de) 2008-09-17
WO2005006341A1 (en) 2005-01-20
KR20060029272A (ko) 2006-04-05
EP1639604A1 (de) 2006-03-29
CN1839446A (zh) 2006-09-27
ATE408882T1 (de) 2008-10-15
JP2007527592A (ja) 2007-09-27
US6876593B2 (en) 2005-04-05
CN1839446B (zh) 2012-09-05
US20050002253A1 (en) 2005-01-06

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