DE602004010055D1 - Nichtflüchtiger Halbleiterspeicher und dessen Betriebsverfahren - Google Patents

Nichtflüchtiger Halbleiterspeicher und dessen Betriebsverfahren

Info

Publication number
DE602004010055D1
DE602004010055D1 DE602004010055T DE602004010055T DE602004010055D1 DE 602004010055 D1 DE602004010055 D1 DE 602004010055D1 DE 602004010055 T DE602004010055 T DE 602004010055T DE 602004010055 T DE602004010055 T DE 602004010055T DE 602004010055 D1 DE602004010055 D1 DE 602004010055D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
operating method
volatile semiconductor
volatile
operating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004010055T
Other languages
English (en)
Other versions
DE602004010055T2 (de
Inventor
Chih-Chieh Yeh
Wen-Jer Tsai
Tao-Cheng Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Publication of DE602004010055D1 publication Critical patent/DE602004010055D1/de
Application granted granted Critical
Publication of DE602004010055T2 publication Critical patent/DE602004010055T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
DE602004010055T 2004-01-14 2004-09-27 Nichtflüchtige Halbleiterspeicherzelle und dessen Betriebsverfahren Active DE602004010055T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/757,073 US7031196B2 (en) 2002-03-29 2004-01-14 Nonvolatile semiconductor memory and operating method of the memory
US757073 2004-01-14

Publications (2)

Publication Number Publication Date
DE602004010055D1 true DE602004010055D1 (de) 2007-12-27
DE602004010055T2 DE602004010055T2 (de) 2008-09-04

Family

ID=34620678

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004010055T Active DE602004010055T2 (de) 2004-01-14 2004-09-27 Nichtflüchtige Halbleiterspeicherzelle und dessen Betriebsverfahren

Country Status (6)

Country Link
US (1) US7031196B2 (de)
EP (1) EP1555673B1 (de)
JP (1) JP4801897B2 (de)
CN (1) CN1670943B (de)
DE (1) DE602004010055T2 (de)
TW (1) TWI247310B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7760554B2 (en) * 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7639542B2 (en) * 2006-05-15 2009-12-29 Apple Inc. Maintenance operations for multi-level data storage cells
US20080031052A1 (en) * 2006-08-01 2008-02-07 Macronix International Co., Ltd. A double-bias erase method for memory devices
US7596030B2 (en) * 2006-08-01 2009-09-29 Macronix International Co., Ltd. Method for improving memory device cycling endurance by providing additional pulse
TWI389321B (zh) * 2008-07-08 2013-03-11 Acer Inc 程式化非揮發性記憶體之方法
KR101466697B1 (ko) * 2008-07-10 2014-12-01 삼성전자주식회사 메모리 장치 및 메모리 데이터 프로그래밍 방법
JP5143655B2 (ja) * 2008-07-22 2013-02-13 スパンション エルエルシー 半導体装置へのデータ書き込み方法、半導体装置
US7715235B2 (en) * 2008-08-25 2010-05-11 Sandisk Corporation Non-volatile memory and method for ramp-down programming
TWI590249B (zh) * 2010-12-03 2017-07-01 半導體能源研究所股份有限公司 積體電路，其驅動方法，及半導體裝置
US9589639B1 (en) 2015-11-04 2017-03-07 International Business Machines Corporation Multiple FET non-volatile memory with default logical state

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5526307A (en) * 1992-01-22 1996-06-11 Macronix International Co., Ltd. Flash EPROM integrated circuit architecture
JP3348466B2 (ja) * 1992-06-09 2002-11-20 セイコーエプソン株式会社 不揮発性半導体装置
JP2901493B2 (ja) 1994-06-27 1999-06-07 日本電気株式会社 半導体記憶装置及びその製造方法
JP3162264B2 (ja) * 1995-05-30 2001-04-25 シャープ株式会社 フラッシュメモリの書換え方法
JP3123924B2 (ja) 1996-06-06 2001-01-15 三洋電機株式会社 不揮発性半導体メモリ
US5768192A (en) 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
US6252799B1 (en) 1997-04-11 2001-06-26 Programmable Silicon Solutions Device with embedded flash and EEPROM memories
US5953255A (en) * 1997-12-24 1999-09-14 Aplus Flash Technology, Inc. Low voltage, low current hot-hole injection erase and hot-electron programmable flash memory with enhanced endurance
US6348711B1 (en) * 1998-05-20 2002-02-19 Saifun Semiconductors Ltd. NROM cell with self-aligned programming and erasure areas
JP2000200842A (ja) 1998-11-04 2000-07-18 Sony Corp 不揮発性半導体記憶装置、製造方法および書き込み方法
US5953251A (en) * 1998-12-18 1999-09-14 Motorola, Inc. Programming method for nonvolatile memories
KR100308192B1 (ko) * 1999-07-28 2001-11-01 윤종용 플래시 메모리 셀들의 과소거를 방지할 수 있는 플래시 메모리장치 및 그것의 소거 방법
US6265268B1 (en) 1999-10-25 2001-07-24 Advanced Micro Devices, Inc. High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device
US6331953B1 (en) * 2000-02-16 2001-12-18 Advanced Micro Devices Intelligent ramped gate and ramped drain erasure for non-volatile memory cells
US6381179B1 (en) 2000-02-24 2002-04-30 Advanced Micro Devices, Inc. Using a negative gate erase to increase the cycling endurance of a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure
JP4834897B2 (ja) 2000-05-02 2011-12-14 ソニー株式会社 不揮発性半導体記憶装置およびその動作方法
US6400610B1 (en) * 2000-07-05 2002-06-04 Motorola, Inc. Memory device including isolated storage elements that utilize hole conduction and method therefor
US7352024B2 (en) * 2001-02-22 2008-04-01 Sharp Kabushiki Kaisha Semiconductor storage device and semiconductor integrated circuit
WO2002097821A1 (fr) * 2001-05-25 2002-12-05 Fujitsu Limited Dispositif de stockage non volatile a semi-conducteur
US6670240B2 (en) * 2001-08-13 2003-12-30 Halo Lsi, Inc. Twin NAND device structure, array operations and fabrication method
JP2003152115A (ja) * 2001-11-16 2003-05-23 Ememory Technology Inc 嵌入式フラッシュメモリ構造及び操作方法
JP2003158207A (ja) * 2001-11-26 2003-05-30 Sony Corp 不揮発性半導体メモリ装置とその動作方法
US6690601B2 (en) * 2002-03-29 2004-02-10 Macronix International Co., Ltd. Nonvolatile semiconductor memory cell with electron-trapping erase state and methods for operating the same
US6657894B2 (en) * 2002-03-29 2003-12-02 Macronix International Co., Ltd, Apparatus and method for programming virtual ground nonvolatile memory cell array without disturbing adjacent cells
US6614694B1 (en) * 2002-04-02 2003-09-02 Macronix International Co., Ltd. Erase scheme for non-volatile memory
US6801453B2 (en) * 2002-04-02 2004-10-05 Macronix International Co., Ltd. Method and apparatus of a read scheme for non-volatile memory

Also Published As

Publication number Publication date
US7031196B2 (en) 2006-04-18
JP4801897B2 (ja) 2011-10-26
US20040156238A1 (en) 2004-08-12
CN1670943B (zh) 2012-06-20
EP1555673B1 (de) 2007-11-14
JP2005203075A (ja) 2005-07-28
TWI247310B (en) 2006-01-11
CN1670943A (zh) 2005-09-21
TW200523930A (en) 2005-07-16
DE602004010055T2 (de) 2008-09-04
EP1555673A1 (de) 2005-07-20

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