DE60106300D1 - Eingangs-/ausgangs-durchgangstestmodus-schaltung - Google Patents

Eingangs-/ausgangs-durchgangstestmodus-schaltung

Info

Publication number
DE60106300D1
DE60106300D1 DE60106300T DE60106300T DE60106300D1 DE 60106300 D1 DE60106300 D1 DE 60106300D1 DE 60106300 T DE60106300 T DE 60106300T DE 60106300 T DE60106300 T DE 60106300T DE 60106300 D1 DE60106300 D1 DE 60106300D1
Authority
DE
Germany
Prior art keywords
input
output
test mode
mode circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60106300T
Other languages
English (en)
Other versions
DE60106300T2 (de
Inventor
S Hui
R Franklin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of DE60106300D1 publication Critical patent/DE60106300D1/de
Application granted granted Critical
Publication of DE60106300T2 publication Critical patent/DE60106300T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE60106300T 2001-01-16 2001-11-28 Eingangs-/ausgangs-durchgangstestmodus-schaltung Expired - Fee Related DE60106300T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US764169 2001-01-16
US09/764,169 US6694463B2 (en) 2001-01-16 2001-01-16 Input/output continuity test mode circuit
PCT/US2001/044694 WO2002057802A1 (en) 2001-01-16 2001-11-28 Input/output continuity test mode circuit

Publications (2)

Publication Number Publication Date
DE60106300D1 true DE60106300D1 (de) 2004-11-11
DE60106300T2 DE60106300T2 (de) 2005-03-24

Family

ID=25069875

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60106300T Expired - Fee Related DE60106300T2 (de) 2001-01-16 2001-11-28 Eingangs-/ausgangs-durchgangstestmodus-schaltung

Country Status (10)

Country Link
US (1) US6694463B2 (de)
EP (1) EP1358498B1 (de)
JP (1) JP2004518130A (de)
KR (1) KR20030075160A (de)
CN (1) CN1254690C (de)
CA (1) CA2432889A1 (de)
DE (1) DE60106300T2 (de)
NO (1) NO20033051L (de)
TW (1) TW523596B (de)
WO (1) WO2002057802A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8572446B2 (en) * 2000-06-30 2013-10-29 Texas Instruments Incorporated Output circuitry with tri-state buffer and comparator circuitry
US6717429B2 (en) * 2000-06-30 2004-04-06 Texas Instruments Incorporated IC having comparator inputs connected to core circuitry and output pad
TW530525B (en) * 2001-07-27 2003-05-01 Via Tech Inc Method of disposing buffer and its chip
US20030131275A1 (en) * 2002-01-09 2003-07-10 Jong-Hong Bae Microcontroller and system having a clock generator
US7032146B2 (en) * 2002-10-29 2006-04-18 International Business Machines Corporation Boundary scan apparatus and interconnect test method
DE10254390B4 (de) * 2002-11-21 2016-05-12 Dr. Johannes Heidenhain Gmbh Schaltungsanordnung sowie mit dieser Schaltungsanordnung ausgestattetes Winkel- bzw. Längenmessgerät
US6944265B2 (en) * 2002-11-25 2005-09-13 Ge Medical Systems Global Technology Company, Llc Image pasting using geometry measurement and a flat-panel detector
KR100746228B1 (ko) 2006-01-25 2007-08-03 삼성전자주식회사 반도체 메모리 모듈 및 반도체 메모리 장치
KR101593603B1 (ko) 2009-01-29 2016-02-15 삼성전자주식회사 반도체 장치의 온도 감지 회로
KR101145312B1 (ko) * 2010-07-06 2012-05-14 에스케이하이닉스 주식회사 반도체 집적회로
JP6171264B2 (ja) * 2012-03-30 2017-08-02 株式会社デンソー 撮像装置
CN103490957B (zh) * 2013-09-24 2016-09-14 深圳市数智国兴信息科技有限公司 一卡通平台系统及其应用方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2659095B2 (ja) 1987-06-30 1997-09-30 富士通株式会社 ゲートアレイ及びメモリを有する半導体集積回路装置
US6304987B1 (en) * 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
JPH0682325B2 (ja) * 1990-05-29 1994-10-19 株式会社東芝 情報処理装置のテスト容易化回路
JPH04159752A (ja) 1990-10-23 1992-06-02 Nec Corp 半導体集積回路及びその装置
JP3059024B2 (ja) * 1993-06-15 2000-07-04 沖電気工業株式会社 半導体記憶回路
US5553070A (en) * 1994-09-13 1996-09-03 Riley; Robert E. Data link module for time division multiplexing control systems
US5699554A (en) * 1994-10-27 1997-12-16 Texas Instruments Incorporated Apparatus for selective operation without optional circuitry
US5561614A (en) * 1995-01-30 1996-10-01 Motorola Inc. Method and apparatus for testing pin isolation for an integrated circuit in a low power mode of operation
US5656953A (en) * 1995-05-31 1997-08-12 Texas Instruments Incorporated Low overhead memory designs for IC terminals
US5589777A (en) * 1995-06-21 1996-12-31 Hewlett-Packard Company Circuit and method for testing a disk drive head assembly without probing
US5744967A (en) * 1995-08-24 1998-04-28 Sorensen; Brent A. Apparatus for detecting intermittent and continuous faults in multiple conductor wiring and terminations for electronic systems
KR0172347B1 (ko) 1995-12-23 1999-03-30 김광호 반도체 메모리장치의 병렬테스트 회로
US5713445A (en) 1996-07-22 1998-02-03 Eaton Corporation Transmission inertia brake with self energizing
EP0852354B1 (de) 1996-11-25 2003-09-03 Texas Instruments Incorporated Integrierte Schaltung
US6060897A (en) * 1997-02-11 2000-05-09 National Semiconductor Corporation Testability method for modularized integrated circuits
US5983377A (en) 1997-11-17 1999-11-09 Ncr Corporation System and circuit for ASIC pin fault testing
US6223313B1 (en) * 1997-12-05 2001-04-24 Lightspeed Semiconductor Corporation Method and apparatus for controlling and observing data in a logic block-based asic
US6119249A (en) 1998-03-27 2000-09-12 Cypress Semiconductor Corp. Memory devices operable in both a normal and a test mode and methods for testing same
US6550031B1 (en) * 1999-10-06 2003-04-15 Advanced Micro Devices Inc. Transparently gathering a chips multiple internal states via scan path and a trigger

Also Published As

Publication number Publication date
US6694463B2 (en) 2004-02-17
DE60106300T2 (de) 2005-03-24
US20020095631A1 (en) 2002-07-18
EP1358498A1 (de) 2003-11-05
CA2432889A1 (en) 2002-07-25
EP1358498B1 (de) 2004-10-06
WO2002057802A1 (en) 2002-07-25
JP2004518130A (ja) 2004-06-17
NO20033051D0 (no) 2003-07-03
TW523596B (en) 2003-03-11
CN1254690C (zh) 2006-05-03
KR20030075160A (ko) 2003-09-22
CN1486431A (zh) 2004-03-31
NO20033051L (no) 2003-07-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee