DE3938826A1 - Verfahren und vorrichtung zum testen eines speichers - Google Patents

Verfahren und vorrichtung zum testen eines speichers

Info

Publication number
DE3938826A1
DE3938826A1 DE3938826A DE3938826A DE3938826A1 DE 3938826 A1 DE3938826 A1 DE 3938826A1 DE 3938826 A DE3938826 A DE 3938826A DE 3938826 A DE3938826 A DE 3938826A DE 3938826 A1 DE3938826 A1 DE 3938826A1
Authority
DE
Germany
Prior art keywords
memory
test
built
data
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE3938826A
Other languages
German (de)
English (en)
Other versions
DE3938826C2 (enExample
Inventor
Hidetada Fukunaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3938826A1 publication Critical patent/DE3938826A1/de
Application granted granted Critical
Publication of DE3938826C2 publication Critical patent/DE3938826C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE3938826A 1988-11-30 1989-11-23 Verfahren und vorrichtung zum testen eines speichers Granted DE3938826A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63302395A JPH02255925A (ja) 1988-11-30 1988-11-30 メモリテスト方法および装置

Publications (2)

Publication Number Publication Date
DE3938826A1 true DE3938826A1 (de) 1990-05-31
DE3938826C2 DE3938826C2 (enExample) 1991-06-27

Family

ID=17908395

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3938826A Granted DE3938826A1 (de) 1988-11-30 1989-11-23 Verfahren und vorrichtung zum testen eines speichers

Country Status (3)

Country Link
US (1) US5109382A (enExample)
JP (1) JPH02255925A (enExample)
DE (1) DE3938826A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0533375A3 (en) * 1991-09-18 1993-06-23 Ncr International Inc. Computer system having memory testing means

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5906816A (en) * 1995-03-16 1999-05-25 University Of Florida Method for treatment of autoimmune diseases
JP3253296B2 (ja) * 1989-12-20 2002-02-04 セイコーエプソン株式会社 記憶装置及びデータ処理装置
EP0470030A3 (en) * 1990-08-02 1993-04-21 International Business Machines Corporation Fast memory power-on diagnostics using direct memory addressing
JP3050326B2 (ja) * 1990-11-30 2000-06-12 日本電気株式会社 半導体集積回路
US5513190A (en) * 1991-10-28 1996-04-30 Sequoia Semiconductor, Inc. Built-in self-test tri-state architecture
TW211094B (en) * 1992-04-30 1993-08-11 American Telephone & Telegraph Built-in self-test network
JP3645578B2 (ja) * 1992-09-17 2005-05-11 テキサス インスツルメンツ インコーポレイテツド スマート・メモリの組込み自己検査のための装置と方法
FR2697663B1 (fr) * 1992-10-30 1995-01-13 Hewett Packard Cy Circuit de test de mémoire.
KR0141432B1 (ko) * 1993-10-01 1998-07-15 기다오까 다까시 반도체 기억장치
US5519659A (en) * 1993-10-01 1996-05-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test
US5617531A (en) * 1993-11-02 1997-04-01 Motorola, Inc. Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
AU5029896A (en) * 1995-03-31 1996-10-16 Intel Corporation Memory testing in a multiple processor computer system
SG89232A1 (en) * 1996-05-14 2002-06-18 Texas Instr Singapore Pte Ltd A process of testing memory parts and equipment for conducting the testing
SG85066A1 (en) * 1996-05-14 2001-12-19 Texas Instr Singapore Pte Ltd Test board and process of testing wide word memoryparts
US5754557A (en) * 1996-10-10 1998-05-19 Hewlett-Packard Co. Method for refreshing a memory, controlled by a memory controller in a computer system, in a self-refresh mode while scanning the memory controller
US5910922A (en) * 1997-08-05 1999-06-08 Integrated Device Technology, Inc. Method for testing data retention in a static random access memory using isolated Vcc supply

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58122700A (ja) * 1982-01-15 1983-07-21 Matsushita Electric Works Ltd メモリチエツク回路
EP0263312A2 (en) * 1986-09-08 1988-04-13 Kabushiki Kaisha Toshiba Semiconductor memory device with a self-testing function

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2508629B2 (ja) * 1985-02-28 1996-06-19 日本電気株式会社 半導体メモリ
JPS6267800A (ja) * 1985-09-20 1987-03-27 Hitachi Ltd 半導体集積回路装置
US4740971A (en) * 1986-02-28 1988-04-26 Advanced Micro Devices, Inc. Tag buffer with testing capability
JP2521774B2 (ja) * 1987-10-02 1996-08-07 株式会社日立製作所 メモリ内蔵型論理ｌｓｉ及びそのｌｓｉの試験方法
FR2623652A1 (fr) * 1987-11-20 1989-05-26 Philips Nv Unite de memoire statique a plusieurs modes de test et ordinateur muni de telles unites
US4903266A (en) * 1988-04-29 1990-02-20 International Business Machines Corporation Memory self-test

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58122700A (ja) * 1982-01-15 1983-07-21 Matsushita Electric Works Ltd メモリチエツク回路
EP0263312A2 (en) * 1986-09-08 1988-04-13 Kabushiki Kaisha Toshiba Semiconductor memory device with a self-testing function

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP-Z: Nikkei Electronics, 06.04.1987 (No. 418), S. 149-163 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0533375A3 (en) * 1991-09-18 1993-06-23 Ncr International Inc. Computer system having memory testing means

Also Published As

Publication number Publication date
US5109382A (en) 1992-04-28
JPH02255925A (ja) 1990-10-16
DE3938826C2 (enExample) 1991-06-27

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee