DE69904320T2 - On-chip schaltung und verfahren zur speicherschaltungs-prüfung - Google Patents

On-chip schaltung und verfahren zur speicherschaltungs-prüfung

Info

Publication number
DE69904320T2
DE69904320T2 DE69904320T DE69904320T DE69904320T2 DE 69904320 T2 DE69904320 T2 DE 69904320T2 DE 69904320 T DE69904320 T DE 69904320T DE 69904320 T DE69904320 T DE 69904320T DE 69904320 T2 DE69904320 T2 DE 69904320T2
Authority
DE
Germany
Prior art keywords
circuit
checking
chip
memory circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69904320T
Other languages
English (en)
Other versions
DE69904320D1 (de
Inventor
M Pierce
L Ingalls
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE69904320D1 publication Critical patent/DE69904320D1/de
Application granted granted Critical
Publication of DE69904320T2 publication Critical patent/DE69904320T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
DE69904320T 1998-06-11 1999-06-11 On-chip schaltung und verfahren zur speicherschaltungs-prüfung Expired - Lifetime DE69904320T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/096,279 US6178532B1 (en) 1998-06-11 1998-06-11 On-chip circuit and method for testing memory devices
PCT/US1999/013029 WO1999065037A1 (en) 1998-06-11 1999-06-11 On-chip circuit and method for testing memory devices

Publications (2)

Publication Number Publication Date
DE69904320D1 DE69904320D1 (de) 2003-01-16
DE69904320T2 true DE69904320T2 (de) 2003-08-28

Family

ID=22256641

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69904320T Expired - Lifetime DE69904320T2 (de) 1998-06-11 1999-06-11 On-chip schaltung und verfahren zur speicherschaltungs-prüfung

Country Status (6)

Country Link
US (2) US6178532B1 (de)
EP (1) EP1084497B1 (de)
KR (1) KR100634034B1 (de)
AU (1) AU4557799A (de)
DE (1) DE69904320T2 (de)
WO (1) WO1999065037A1 (de)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6178532B1 (en) * 1998-06-11 2001-01-23 Micron Technology, Inc. On-chip circuit and method for testing memory devices
US6966021B2 (en) * 1998-06-16 2005-11-15 Janusz Rajski Method and apparatus for at-speed testing of digital circuits
GB2344975B (en) * 1998-12-14 2004-03-10 Inventec Corp Communication port testing module and method thereof
US6357018B1 (en) * 1999-01-26 2002-03-12 Dell Usa, L.P. Method and apparatus for determining continuity and integrity of a RAMBUS channel in a computer system
US7493540B1 (en) 1999-11-23 2009-02-17 Jansuz Rajski Continuous application and decompression of test patterns to a circuit-under-test
US6684358B1 (en) * 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
JP3845016B2 (ja) * 1999-11-23 2006-11-15 メンター・グラフィクス・コーポレーション テスト中回路技術分野へのテストパターンの連続的な適用およびデコンプレッション
US9134370B2 (en) 1999-11-23 2015-09-15 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US9664739B2 (en) 1999-11-23 2017-05-30 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6353842B1 (en) * 1999-11-23 2002-03-05 Janusz Rajski Method for synthesizing linear finite state machines
US8533547B2 (en) * 1999-11-23 2013-09-10 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6557129B1 (en) * 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
US6874109B1 (en) * 1999-11-23 2005-03-29 Janusz Rajski Phase shifter with reduced linear dependency
US6327687B1 (en) 1999-11-23 2001-12-04 Janusz Rajski Test pattern compression for an integrated circuit test environment
US6275443B1 (en) * 2000-08-30 2001-08-14 Micron Technology, Inc. Latched row or column select enable driver
JP4125492B2 (ja) * 2001-02-01 2008-07-30 株式会社日立製作所 半導体集積回路装置とテスト方法及び半導体集積回路装置の製造方法
US6760872B2 (en) * 2001-03-19 2004-07-06 Cypress Semiconductor Corp. Configurable and memory architecture independent memory built-in self test
US6404250B1 (en) * 2001-03-28 2002-06-11 Infineon Technologies Richmond, Lp On-chip circuits for high speed memory testing with a slow memory tester
DE10129771A1 (de) * 2001-06-20 2003-01-23 Infineon Technologies Ag Testanordnung zum parallelen Funktionstest von Halbleiterspeicherbausteinen und Testverfahren
DE10130785C2 (de) * 2001-06-26 2003-04-30 Infineon Technologies Ag Speicherbaustein und Vorrichtung zum Testen eines Speicherbausteins
ITRM20010556A1 (it) * 2001-09-12 2003-03-12 Micron Technology Inc Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati.
US20030084390A1 (en) * 2001-10-26 2003-05-01 Mentor Graphics Corporation At-speed test using on-chip controller
JP2004046927A (ja) * 2002-07-09 2004-02-12 Elpida Memory Inc 半導体記憶装置
US7183792B2 (en) * 2003-04-01 2007-02-27 Micron Technology, Inc. Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same
KR100498502B1 (ko) * 2003-06-09 2005-07-01 삼성전자주식회사 기준 데이터를 스택시켜 레이턴시를 보상하는 반도체메모리 장치 및 그 테스트 방법
DE10331543B4 (de) * 2003-07-11 2007-11-08 Qimonda Ag Verfahren zum Testen einer zu testenden Schaltungseinheit und Schaltungsanordnung zur Durchführung des Verfahrens
US7210059B2 (en) * 2003-08-19 2007-04-24 Micron Technology, Inc. System and method for on-board diagnostics of memory modules
US7310752B2 (en) * 2003-09-12 2007-12-18 Micron Technology, Inc. System and method for on-board timing margin testing of memory modules
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
KR100510553B1 (ko) * 2003-10-30 2005-08-26 삼성전자주식회사 메모리 장치 및 메모리 장치의 입력 신호 제어 방법
US7818646B1 (en) * 2003-11-12 2010-10-19 Hewlett-Packard Development Company, L.P. Expectation based event verification
US7321951B2 (en) * 2003-11-17 2008-01-22 Micron Technology, Inc. Method for testing flash memory power loss recovery
US7216196B2 (en) * 2003-12-29 2007-05-08 Micron Technology, Inc. Memory hub and method for memory system performance monitoring
US7310748B2 (en) * 2004-06-04 2007-12-18 Micron Technology, Inc. Memory hub tester interface and method for use thereof
US7375326B2 (en) * 2004-06-21 2008-05-20 Applied Materials, Israel, Ltd. Method and system for focusing a charged particle beam
US7518602B2 (en) * 2004-12-06 2009-04-14 Semiconductor Energy Laboratory Co., Ltd. Test circuit and display device having the same
US7555690B1 (en) * 2004-12-23 2009-06-30 Xilinx, Inc. Device for and method of coupling test signals to a device under test
GB0519363D0 (en) * 2005-09-22 2005-11-02 Advanced Risc Mach Ltd Error propagation in integrated circuits
US7599242B2 (en) * 2005-09-28 2009-10-06 Hynix Semiconductor Inc. Test circuit for multi-port memory device
KR100842757B1 (ko) 2005-09-28 2008-07-01 주식회사 하이닉스반도체 반도체 메모리 장치
KR100772724B1 (ko) * 2005-09-28 2007-11-02 주식회사 하이닉스반도체 반도체 메모리 장치
JP4354452B2 (ja) * 2005-11-18 2009-10-28 シャープ株式会社 半導体集積回路及びその検査方法
US7669090B2 (en) * 2006-05-18 2010-02-23 Kabushiki Kaisha Toshiba Apparatus and method for verifying custom IC
US7430487B2 (en) * 2006-09-06 2008-09-30 International Business Machines Corporation System and method for implementing a programmable DMA master with data checking utilizing a drone system controller
KR100837802B1 (ko) * 2006-09-13 2008-06-13 주식회사 하이닉스반도체 데이터 입출력 오류 검출 기능을 갖는 반도체 메모리 장치
KR100825779B1 (ko) * 2006-09-28 2008-04-29 삼성전자주식회사 반도체 메모리장치 및 이에 대한 웨이퍼 레벨 테스트 방법
KR100850204B1 (ko) * 2006-11-04 2008-08-04 삼성전자주식회사 고속 반도체 메모리 장치를 테스트하기 위한 고주파 커맨드 신호 및 어드레스 신호 생성 방법 및 장치
US7564380B2 (en) * 2007-08-02 2009-07-21 General Electric Company Systems and methods for storing test data and accessing test data
US7668025B2 (en) * 2007-10-04 2010-02-23 Hynix Semiconductor Inc. Input circuit of semiconductor memory apparatus and control method of the same
KR101431272B1 (ko) * 2008-01-30 2014-08-20 엘지전자 주식회사 외장형 스토리지가 연결 접속된 보안기기에서의 비트레이트 조정 장치 및 방법
JP5196538B2 (ja) * 2008-02-12 2013-05-15 ルネサスエレクトロニクス株式会社 半導体集積回路の設計方法、半導体集積回路の設計プログラム、及び半導体集積回路
KR100951567B1 (ko) * 2008-02-29 2010-04-09 주식회사 하이닉스반도체 데이터 전달의 신뢰성을 보장하기 위한 반도체 메모리 장치
KR20120078998A (ko) 2011-01-03 2012-07-11 에스케이하이닉스 주식회사 비휘발성 메모리 장치
KR20130050776A (ko) * 2011-11-08 2013-05-16 에스케이하이닉스 주식회사 반도체 장치와 반도체 장치를 포함하는 반도체 시스템 및 그 동작방법
US9026870B2 (en) * 2012-07-27 2015-05-05 Samsung Electronics Co., Ltd. Memory module and a memory test system for testing the same
JP6341795B2 (ja) * 2014-08-05 2018-06-13 ルネサスエレクトロニクス株式会社 マイクロコンピュータ及びマイクロコンピュータシステム
US10691094B1 (en) 2018-12-12 2020-06-23 International Business Machines Corporation Techniques for indicating the status of power devices of a power subsystem
US10790039B1 (en) * 2019-09-26 2020-09-29 Micron Technology, Inc. Semiconductor device having a test circuit
US20230230651A1 (en) * 2022-01-19 2023-07-20 Changxin Memory Technologies, Inc. Method and device for testing memory chip, storage medium and electronic device
CN117059155A (zh) * 2022-05-06 2023-11-14 长鑫存储技术有限公司 测试电路检查方法、测试平台、存储介质和测试系统

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4183095A (en) * 1978-09-01 1980-01-08 Ncr Corporation High density memory device
US4669082A (en) * 1985-05-09 1987-05-26 Halliburton Company Method of testing and addressing a magnetic core memory
JPH02146199A (ja) 1988-11-28 1990-06-05 Mitsubishi Electric Corp 半導体記憶装置のテスト回路
US5231605A (en) 1991-01-31 1993-07-27 Micron Technology, Inc. DRAM compressed data test mode with expected data
US5367522A (en) * 1991-02-21 1994-11-22 Canon Kabushiki Kaisha Multimedia communicating apparatus
US5533194A (en) * 1994-12-28 1996-07-02 International Business Machines Corporation Hardware-assisted high speed memory test apparatus and method
EP0744755A1 (de) 1995-05-25 1996-11-27 International Business Machines Corporation Prüfungsverfahren und Vorrichtung für Speicherschaltungen auf Halbleitersubstrat
US5568437A (en) 1995-06-20 1996-10-22 Vlsi Technology, Inc. Built-in self test for integrated circuits having read/write memory
DE19680782C2 (de) * 1995-07-26 2002-11-21 Advantest Corp Hochgeschwindigkeits- Mustergenerierungsverfahren und unter Verwendung dieses Verfahrens arbeitender Hochgeschwindigkeits-Mustergenerator
JP2848300B2 (ja) * 1995-12-27 1999-01-20 日本電気株式会社 不揮発性半導体記憶装置
TW343282B (en) * 1996-06-14 1998-10-21 Adoban Tesuto Kk Testing device for a semiconductor device
US5812562A (en) * 1996-11-15 1998-09-22 Samsung Electronics Company, Ltd. Low cost emulation scheme implemented via clock control using JTAG controller in a scan environment
JPH10171676A (ja) * 1996-12-10 1998-06-26 Toshiba Corp マイクロプロセッサのテスト容易化回路
US5966388A (en) * 1997-01-06 1999-10-12 Micron Technology, Inc. High-speed test system for a memory device
US5757705A (en) 1997-01-22 1998-05-26 Micron Technology, Inc. SDRAM clocking test mode
US6014759A (en) * 1997-06-13 2000-01-11 Micron Technology, Inc. Method and apparatus for transferring test data from a memory array
US6002620A (en) * 1998-01-09 1999-12-14 Information Storage Devices, Inc. Method and apparatus of column redundancy for non-volatile analog and multilevel memory
US6014763A (en) * 1998-01-15 2000-01-11 International Business Machines Corporation At-speed scan testing
US6058056A (en) * 1998-04-30 2000-05-02 Micron Technology, Inc. Data compression circuit and method for testing memory devices
US6067649A (en) * 1998-06-10 2000-05-23 Compaq Computer Corporation Method and apparatus for a low power self test of a memory subsystem
US6178532B1 (en) * 1998-06-11 2001-01-23 Micron Technology, Inc. On-chip circuit and method for testing memory devices

Also Published As

Publication number Publication date
US20010013110A1 (en) 2001-08-09
AU4557799A (en) 1999-12-30
EP1084497A1 (de) 2001-03-21
DE69904320D1 (de) 2003-01-16
US6178532B1 (en) 2001-01-23
WO1999065037A1 (en) 1999-12-16
EP1084497B1 (de) 2002-12-04
KR20010071455A (ko) 2001-07-28
KR100634034B1 (ko) 2006-10-17
US6536004B2 (en) 2003-03-18

Similar Documents

Publication Publication Date Title
DE69904320T2 (de) On-chip schaltung und verfahren zur speicherschaltungs-prüfung
DE69835780D1 (de) Halbleiter-Speicherbauelement und Verfahren zu seiner Herstellung
DE69934581D1 (de) Kompositschaltungsschutzvorrichtung und verfahren zur herstellung derselben
GB9928012D0 (en) Chip type electronic part and method for the manufacture thereof
DE60205817D1 (de) Verfahren zur Erfassung und Beseitigung des Memory-Effektes
DE69942640D1 (de) Halbleiterspeichervorrichtung und Speicherverfahren dafür
DE69941879D1 (de) Feldeffekt-halbleiterbauelement und verfahren zu dessen herstellung
DE1220503T1 (de) Verfahren und schaltung zur erfassung
DE69942007D1 (de) System und verfahren zum identifizieren von endlichen automaten und überprüfung des schaltkreisdesigns
DE69838362D1 (de) Verbesserte integrierte Mehrschicht-Testflächen und Methode dafür
DE69706043D1 (de) Integrierte schaltungsschutzanordnung und verfahren
DE59907605D1 (de) Schaltanordnung und Verfahren zu ihrer Herstellung
DE69941874D1 (de) Optielektronisches bauelement und herstellungsverfahren
DE69905929D1 (de) Selbstbedienungsterminal und verfahren zu seinem betrieb
DE69833756D1 (de) Elektronisches bauelement und verfahren zu seiner herstellung
DE69822918D1 (de) Elektronisches Teil und Verfahren zu seiner Herstellung
DE59709441D1 (de) Verfahren zur Initialisierung und Überwachung wenigstens eines elektrischen Verbrauchers und Schaltungsanordnung
DE69921926D1 (de) Bilderzeugungsgerät und Verfahren
DE69839906D1 (de) Herstellungsverfahren für eine integrierte Schaltung
DE69937428D1 (de) Gleichtaktrückkopplungsschaltung und Verfahren
DE69831005D1 (de) Kreislauf und verfahren zur verwaltung der leistungsverteilung
DE69830967D1 (de) Verfahren und System zur Prüfung einer integrierten Schaltung
DE59905612D1 (de) Integrierte Schaltung und Verfahren zu ihrer Prüfung
DE50000925D1 (de) Vorrichtung und verfahren für den eingebauten selbsttest einer elektronischen schaltung
DE59808510D1 (de) Verfahren und Schaltungsanordnung zur Prüfung von Münzen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8381 Inventor (new situation)

Inventor name: PIERCE, KIM M., MERIDIAN, IDAHO, US

Inventor name: INGALLS, ., CHARLES L., MERIDIAN, IDAHO, US