DE69838362D1 - Verbesserte integrierte Mehrschicht-Testflächen und Methode dafür - Google Patents

Verbesserte integrierte Mehrschicht-Testflächen und Methode dafür

Info

Publication number
DE69838362D1
DE69838362D1 DE69838362T DE69838362T DE69838362D1 DE 69838362 D1 DE69838362 D1 DE 69838362D1 DE 69838362 T DE69838362 T DE 69838362T DE 69838362 T DE69838362 T DE 69838362T DE 69838362 D1 DE69838362 D1 DE 69838362D1
Authority
DE
Germany
Prior art keywords
doing
integrated multi
test surfaces
layer test
enhanced integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69838362T
Other languages
English (en)
Other versions
DE69838362T2 (de
Inventor
Frank Alswede
Ron Mendelson
William Davies
Frank Prein
Ronald Hoyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
International Business Machines Corp
Original Assignee
Infineon Technologies AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, International Business Machines Corp filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE69838362D1 publication Critical patent/DE69838362D1/de
Publication of DE69838362T2 publication Critical patent/DE69838362T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/923—Active solid-state devices, e.g. transistors, solid-state diodes with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69838362T 1997-05-21 1998-05-21 Verbesserte integrierte Mehrschicht-Testflächen und Methode dafür Expired - Lifetime DE69838362T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/861,465 US5917197A (en) 1997-05-21 1997-05-21 Integrated multi-layer test pads
US861465 1997-05-21

Publications (2)

Publication Number Publication Date
DE69838362D1 true DE69838362D1 (de) 2007-10-18
DE69838362T2 DE69838362T2 (de) 2008-05-21

Family

ID=25335874

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69838362T Expired - Lifetime DE69838362T2 (de) 1997-05-21 1998-05-21 Verbesserte integrierte Mehrschicht-Testflächen und Methode dafür

Country Status (7)

Country Link
US (2) US5917197A (de)
EP (1) EP0880173B1 (de)
JP (1) JP4199846B2 (de)
KR (1) KR19980087238A (de)
CN (1) CN1156902C (de)
DE (1) DE69838362T2 (de)
TW (1) TW396482B (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
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JP3156896B2 (ja) * 1994-01-28 2001-04-16 富士通株式会社 半導体装置の製造方法およびかかる製造方法により製造された半導体装置
US5917197A (en) * 1997-05-21 1999-06-29 Siemens Aktiengesellschaft Integrated multi-layer test pads
US6133582A (en) 1998-05-14 2000-10-17 Lightspeed Semiconductor Corporation Methods and apparatuses for binning partially completed integrated circuits based upon test results
US6380729B1 (en) * 1999-02-16 2002-04-30 Alien Technology Corporation Testing integrated circuit dice
US6313541B1 (en) * 1999-06-08 2001-11-06 Winbond Electronics Corp. Bone-pad with pad edge strengthening structure
DE19958906A1 (de) * 1999-12-07 2001-07-05 Infineon Technologies Ag Herstellung von integrierten Schaltungen
KR20020021123A (ko) * 2000-04-12 2002-03-18 롤페스 요하네스 게라투스 알베르투스 반도체 디바이스 및 이의 제조 방법
KR100822916B1 (ko) * 2000-04-12 2008-04-16 엔엑스피 비 브이 반도체 장치 및 그 전기적 파라미터 테스트 방법
US6495918B1 (en) 2000-09-05 2002-12-17 Infineon Technologies Ag Chip crack stop design for semiconductor chips
TW546804B (en) * 2001-11-16 2003-08-11 Advanced Semiconductor Eng Electric testing method for bumps
JP4426166B2 (ja) * 2002-11-01 2010-03-03 ユー・エム・シー・ジャパン株式会社 半導体装置の設計方法、半導体装置設計用プログラム、及び半導体装置
KR100543867B1 (ko) * 2003-01-30 2006-01-20 동부아남반도체 주식회사 메모리 혹은 임베디드 메모리 디바이스에서 쉽게 결함을 찾는 와이드 메모리 패턴
US6787803B1 (en) * 2003-06-24 2004-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Test patterns for measurement of low-k dielectric cracking thresholds
US7223616B2 (en) * 2004-06-04 2007-05-29 Lsi Corporation Test structures in unused areas of semiconductor integrated circuits and methods for designing the same
DE102005041283B4 (de) * 2005-08-31 2017-12-14 Globalfoundries Inc. Verfahren und Halbleiterstruktur zur Überwachung der Herstellung von Verbindungsstrukturen und Kontakten in einem Halbleiterbauelement
US8436635B2 (en) * 2009-09-01 2013-05-07 Texas Instruments Incorporated Semiconductor wafer having test modules including pin matrix selectable test devices
CN102832201B (zh) * 2011-06-15 2015-03-11 中芯国际集成电路制造(上海)有限公司 测试结构及测试方法
US9768134B2 (en) 2015-01-29 2017-09-19 Micron Technology, Inc. Methods of forming conductive materials on semiconductor devices, and methods of forming electrical interconnects
CN205959980U (zh) * 2016-08-26 2017-02-15 合肥鑫晟光电科技有限公司 膜层测试结构及阵列基板
KR102401664B1 (ko) 2018-02-06 2022-05-24 주식회사 히타치하이테크 프로브 모듈 및 프로브
CN111566790B (zh) 2018-02-06 2024-04-19 株式会社日立高新技术 半导体装置的评价装置
KR20200096600A (ko) * 2018-02-06 2020-08-12 주식회사 히타치하이테크 반도체 장치의 제조 방법
US10692841B2 (en) * 2018-06-27 2020-06-23 Micron Technology, Inc. Semiconductor devices having through-stack interconnects for facilitating connectivity testing
TW202105671A (zh) * 2019-02-22 2021-02-01 加拿大商弗瑞爾公司 微裝置匣結構
US11821937B2 (en) 2021-08-12 2023-11-21 Changxin Memory Technologies, Inc. Semiconductor base plate and test method thereof
CN113658939B (zh) * 2021-08-12 2023-10-03 长鑫存储技术有限公司 半导体基板及其测试方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714105B2 (ja) * 1986-05-19 1995-02-15 日本電装株式会社 混成集積回路基板及びその製造方法
US5206181A (en) * 1991-06-03 1993-04-27 Motorola, Inc. Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing
US5149674A (en) * 1991-06-17 1992-09-22 Motorola, Inc. Method for making a planar multi-layer metal bonding pad
US5366906A (en) * 1992-10-16 1994-11-22 Martin Marietta Corporation Wafer level integration and testing
JP2776457B2 (ja) * 1992-12-29 1998-07-16 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体デバイスのクラックストップ形成方法及び半導体デバイス
KR0136684B1 (en) * 1993-06-01 1998-04-29 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
US5393703A (en) * 1993-11-12 1995-02-28 Motorola, Inc. Process for forming a conductive layer for semiconductor devices
US5554940A (en) * 1994-07-05 1996-09-10 Motorola, Inc. Bumped semiconductor device and method for probing the same
US5696030A (en) * 1994-09-30 1997-12-09 International Business Machines Corporation Integrated circuit contacts having improved electromigration characteristics and fabrication methods therefor
US5598009A (en) * 1994-11-15 1997-01-28 Advanced Micro Devices, Inc. Hot carrier injection test structure and testing technique for statistical evaluation
US5686759A (en) * 1995-09-29 1997-11-11 Intel Corporation Integrated circuit package with permanent identification of device characteristics and method for adding the same
WO1997036330A1 (en) * 1996-03-28 1997-10-02 Intel Corporation Memory cell design with vertically stacked crossovers
US5917197A (en) * 1997-05-21 1999-06-29 Siemens Aktiengesellschaft Integrated multi-layer test pads

Also Published As

Publication number Publication date
US5981302A (en) 1999-11-09
KR19980087238A (ko) 1998-12-05
TW396482B (en) 2000-07-01
CN1156902C (zh) 2004-07-07
EP0880173A3 (de) 1999-10-20
CN1199925A (zh) 1998-11-25
EP0880173B1 (de) 2007-09-05
US5917197A (en) 1999-06-29
EP0880173A2 (de) 1998-11-25
DE69838362T2 (de) 2008-05-21
JPH10335398A (ja) 1998-12-18
JP4199846B2 (ja) 2008-12-24

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,, US

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8328 Change in the person/name/address of the agent

Representative=s name: EPPING HERMANN FISCHER, PATENTANWALTSGESELLSCHAFT

8364 No opposition during term of opposition