JPH02255925A - メモリテスト方法および装置 - Google Patents

メモリテスト方法および装置

Info

Publication number
JPH02255925A
JPH02255925A JP63302395A JP30239588A JPH02255925A JP H02255925 A JPH02255925 A JP H02255925A JP 63302395 A JP63302395 A JP 63302395A JP 30239588 A JP30239588 A JP 30239588A JP H02255925 A JPH02255925 A JP H02255925A
Authority
JP
Japan
Prior art keywords
memory
test
test function
built
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63302395A
Other languages
English (en)
Japanese (ja)
Inventor
Hidetada Fukunaka
福中　秀忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63302395A priority Critical patent/JPH02255925A/ja
Priority to US07/439,838 priority patent/US5109382A/en
Priority to DE3938826A priority patent/DE3938826A1/de
Publication of JPH02255925A publication Critical patent/JPH02255925A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP63302395A 1988-11-30 1988-11-30 メモリテスト方法および装置 Pending JPH02255925A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP63302395A JPH02255925A (ja) 1988-11-30 1988-11-30 メモリテスト方法および装置
US07/439,838 US5109382A (en) 1988-11-30 1989-11-21 Method and apparatus for testing a memory
DE3938826A DE3938826A1 (de) 1988-11-30 1989-11-23 Verfahren und vorrichtung zum testen eines speichers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63302395A JPH02255925A (ja) 1988-11-30 1988-11-30 メモリテスト方法および装置

Publications (1)

Publication Number Publication Date
JPH02255925A true JPH02255925A (ja) 1990-10-16

Family

ID=17908395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63302395A Pending JPH02255925A (ja) 1988-11-30 1988-11-30 メモリテスト方法および装置

Country Status (3)

Country Link
US (1) US5109382A (enExample)
JP (1) JPH02255925A (enExample)
DE (1) DE3938826A1 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5906816A (en) * 1995-03-16 1999-05-25 University Of Florida Method for treatment of autoimmune diseases
JP3253296B2 (ja) * 1989-12-20 2002-02-04 セイコーエプソン株式会社 記憶装置及びデータ処理装置
JPH04271445A (ja) * 1990-08-02 1992-09-28 Internatl Business Mach Corp <Ibm> メモリ・テスト装置
JP3050326B2 (ja) * 1990-11-30 2000-06-12 日本電気株式会社 半導体集積回路
EP0533375A3 (en) * 1991-09-18 1993-06-23 Ncr International Inc. Computer system having memory testing means
US5513190A (en) * 1991-10-28 1996-04-30 Sequoia Semiconductor, Inc. Built-in self-test tri-state architecture
TW211094B (en) * 1992-04-30 1993-08-11 American Telephone & Telegraph Built-in self-test network
JP3645578B2 (ja) * 1992-09-17 2005-05-11 テキサス インスツルメンツ インコーポレイテツド スマート・メモリの組込み自己検査のための装置と方法
FR2697663B1 (fr) * 1992-10-30 1995-01-13 Hewett Packard Cy Circuit de test de mémoire.
US5519659A (en) * 1993-10-01 1996-05-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test
KR0141432B1 (ko) * 1993-10-01 1998-07-15 기다오까 다까시 반도체 기억장치
US5617531A (en) * 1993-11-02 1997-04-01 Motorola, Inc. Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
AU5029896A (en) * 1995-03-31 1996-10-16 Intel Corporation Memory testing in a multiple processor computer system
SG89232A1 (en) * 1996-05-14 2002-06-18 Texas Instr Singapore Pte Ltd A process of testing memory parts and equipment for conducting the testing
SG85066A1 (en) * 1996-05-14 2001-12-19 Texas Instr Singapore Pte Ltd Test board and process of testing wide word memoryparts
US5754557A (en) * 1996-10-10 1998-05-19 Hewlett-Packard Co. Method for refreshing a memory, controlled by a memory controller in a computer system, in a self-refresh mode while scanning the memory controller
US5910922A (en) * 1997-08-05 1999-06-08 Integrated Device Technology, Inc. Method for testing data retention in a static random access memory using isolated Vcc supply

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58122700A (ja) * 1982-01-15 1983-07-21 Matsushita Electric Works Ltd メモリチエツク回路
JP2508629B2 (ja) * 1985-02-28 1996-06-19 日本電気株式会社 半導体メモリ
JPS6267800A (ja) * 1985-09-20 1987-03-27 Hitachi Ltd 半導体集積回路装置
US4740971A (en) * 1986-02-28 1988-04-26 Advanced Micro Devices, Inc. Tag buffer with testing capability
KR910001534B1 (ko) * 1986-09-08 1991-03-15 가부시키가이샤 도시바 반도체기억장치
JP2521774B2 (ja) * 1987-10-02 1996-08-07 株式会社日立製作所 メモリ内蔵型論理ｌｓｉ及びそのｌｓｉの試験方法
FR2623652A1 (fr) * 1987-11-20 1989-05-26 Philips Nv Unite de memoire statique a plusieurs modes de test et ordinateur muni de telles unites
US4903266A (en) * 1988-04-29 1990-02-20 International Business Machines Corporation Memory self-test

Also Published As

Publication number Publication date
DE3938826C2 (enExample) 1991-06-27
US5109382A (en) 1992-04-28
DE3938826A1 (de) 1990-05-31

Similar Documents

Publication Publication Date Title
JPH02255925A (ja) メモリテスト方法および装置
US5925142A (en) Self-test RAM using external synchronous clock
JPH09128998A (ja) テスト回路
WO1999005682A1 (en) Method and apparatus for reading compressed test data from memory devices
JPH1196755A (ja) Ｄｒａｍ搭載の集積回路
KR940002904B1 (ko) 데이타 처리 시스템 및 이 시스템에 있어서의 다수 메모리 어레이 테스팅 방법
JPH08272733A (ja) Ｄｍａコントローラ
JP4334066B2 (ja) パターン発生器及び電気部品試験装置
JP2934608B2 (ja) 半導体メモリ試験方法及びその装置
JPH0535391B2 (enExample)
Raghavachari Circuit Pack BIST from System to Factory-The MCERT Chip
US6950921B2 (en) Method for operating an integrated memory unit partitioned by an external control signal
JPS6041150A (ja) 記憶装置制御方式
JPS59101100A (ja) 記憶装置の試験方式
JPS5917039Y2 (ja) Ｒｏｍチエツカ−
JP2671210B2 (ja) 半導体テスターのパターン発生器
JP2002008391A (ja) 半導体試験装置及びこれを用いる試験方法
TW202343465A (zh) 測試電路與於記憶體傾印操作中讀取記憶體裝置之資料之方法
KR920009060B1 (ko) 메모리 시험장치
JPH07281992A (ja) Ｄｍａコントローラ
JPS6011941A (ja) デ−タ処理装置
JP2001067244A (ja) オンチップメモリモジュール
JPS634500A (ja) テスト回路付きｒａｍ装置
JPS6228874B2 (enExample)
JPH0218647A (ja) キャシュメモリテスト方法