DE3886568D1 - Halbleiter-Speichereinrichtung mit Adressgenerator. - Google Patents

Halbleiter-Speichereinrichtung mit Adressgenerator.

Info

Publication number
DE3886568D1
DE3886568D1 DE88102847T DE3886568T DE3886568D1 DE 3886568 D1 DE3886568 D1 DE 3886568D1 DE 88102847 T DE88102847 T DE 88102847T DE 3886568 T DE3886568 T DE 3886568T DE 3886568 D1 DE3886568 D1 DE 3886568D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
address generator
address
generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88102847T
Other languages
English (en)
Other versions
DE3886568T2 (de
Inventor
Shigeki Demura
Toshio Oura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE3886568D1 publication Critical patent/DE3886568D1/de
Application granted granted Critical
Publication of DE3886568T2 publication Critical patent/DE3886568T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
DE3886568T 1987-02-27 1988-02-25 Halbleiter-Speichereinrichtung mit Adressgenerator. Expired - Fee Related DE3886568T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4574287A JPH0715800B2 (ja) 1987-02-27 1987-02-27 記憶回路

Publications (2)

Publication Number Publication Date
DE3886568D1 true DE3886568D1 (de) 1994-02-10
DE3886568T2 DE3886568T2 (de) 1994-06-16

Family

ID=12727770

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3886568T Expired - Fee Related DE3886568T2 (de) 1987-02-27 1988-02-25 Halbleiter-Speichereinrichtung mit Adressgenerator.

Country Status (4)

Country Link
US (1) US4841487A (de)
EP (1) EP0281867B1 (de)
JP (1) JPH0715800B2 (de)
DE (1) DE3886568T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5313678A (en) * 1993-01-08 1994-05-24 Redewill Frances H Acoustical pillow
DE4302754C1 (de) * 1993-02-01 1994-06-16 Siemens Ag Monolithisch integrierte Datenspeicheranordnung und Verfahren zu deren Betrieb
US5815024A (en) * 1993-06-11 1998-09-29 Altera Corporation Look-up table using multi-level decode
US5438295A (en) 1993-06-11 1995-08-01 Altera Corporation Look-up table using multi-level decode
GB9417271D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Memory device
US6640296B2 (en) * 2002-03-07 2003-10-28 Nokia Corporation Data processing method and device for parallel stride access
US7403446B1 (en) 2005-09-27 2008-07-22 Cypress Semiconductor Corporation Single late-write for standard synchronous SRAMs

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4233675A (en) * 1979-06-08 1980-11-11 National Semiconductor Corporation X Sense AMP memory
US4739497A (en) * 1981-05-29 1988-04-19 Hitachi, Ltd. Semiconductor memory
JPS5873097A (ja) * 1981-10-27 1983-05-02 Nec Corp デコ−ダ−回路
GB2132843B (en) * 1982-12-07 1986-05-29 Itt Ind Ltd Semiconductor memory
JPS6059588A (ja) * 1983-09-12 1985-04-05 Hitachi Ltd 半導体記憶装置
NL8500434A (nl) * 1985-02-15 1986-09-01 Philips Nv Geintegreerde geheugenschakeling met blokselektie.
JPS6221357A (ja) * 1985-07-22 1987-01-29 Toshiba Corp メモリシステム

Also Published As

Publication number Publication date
JPS63213194A (ja) 1988-09-06
EP0281867A3 (en) 1990-10-17
DE3886568T2 (de) 1994-06-16
US4841487A (en) 1989-06-20
JPH0715800B2 (ja) 1995-02-22
EP0281867A2 (de) 1988-09-14
EP0281867B1 (de) 1993-12-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee