DE3887180D1 - Halbleiter-Speichereinrichtung mit Schutzzellen. - Google Patents

Halbleiter-Speichereinrichtung mit Schutzzellen.

Info

Publication number
DE3887180D1
DE3887180D1 DE88102848T DE3887180T DE3887180D1 DE 3887180 D1 DE3887180 D1 DE 3887180D1 DE 88102848 T DE88102848 T DE 88102848T DE 3887180 T DE3887180 T DE 3887180T DE 3887180 D1 DE3887180 D1 DE 3887180D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
protective cells
protective
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88102848T
Other languages
English (en)
Other versions
DE3887180T2 (de
Inventor
Tatsunori C O Nec Cor Murotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE3887180D1 publication Critical patent/DE3887180D1/de
Application granted granted Critical
Publication of DE3887180T2 publication Critical patent/DE3887180T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
DE88102848T 1987-02-26 1988-02-25 Halbleiter-Speichereinrichtung mit Schutzzellen. Expired - Fee Related DE3887180T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62044296A JPH0632213B2 (ja) 1987-02-26 1987-02-26 半導体メモリ

Publications (2)

Publication Number Publication Date
DE3887180D1 true DE3887180D1 (de) 1994-03-03
DE3887180T2 DE3887180T2 (de) 1994-05-05

Family

ID=12687546

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88102848T Expired - Fee Related DE3887180T2 (de) 1987-02-26 1988-02-25 Halbleiter-Speichereinrichtung mit Schutzzellen.

Country Status (4)

Country Link
US (1) US4875194A (de)
EP (1) EP0281868B1 (de)
JP (1) JPH0632213B2 (de)
DE (1) DE3887180T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2582439B2 (ja) * 1989-07-11 1997-02-19 富士通株式会社 書き込み可能な半導体記憶装置
US6831317B2 (en) 1995-11-09 2004-12-14 Hitachi, Ltd. System with meshed power and signal buses on cell array
US6512257B2 (en) 1995-11-09 2003-01-28 Hitachi, Inc. System with meshed power and signal buses on cell array
JP3869045B2 (ja) * 1995-11-09 2007-01-17 株式会社日立製作所 半導体記憶装置
US6310810B1 (en) * 2000-07-14 2001-10-30 Raj Kumar Jain High-speed sense amplifier
US6449202B1 (en) * 2001-08-14 2002-09-10 International Business Machines Corporation DRAM direct sensing scheme

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6032911B2 (ja) * 1979-07-26 1985-07-31 株式会社東芝 半導体記憶装置
JPS5683899A (en) * 1979-12-12 1981-07-08 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory device
US4327426A (en) * 1980-02-11 1982-04-27 Texas Instruments, Incorporated Column decoder discharge for semiconductor memory
JPS58111183A (ja) * 1981-12-25 1983-07-02 Hitachi Ltd ダイナミツクｒａｍ集積回路装置
FR2528613B1 (fr) * 1982-06-09 1991-09-20 Hitachi Ltd Memoire a semi-conducteurs
NL8300497A (nl) * 1983-02-10 1984-09-03 Philips Nv Halfgeleiderinrichting met niet-vluchtige geheugentransistors.
JPS6095799A (ja) * 1983-10-31 1985-05-29 Nec Corp プログラマブル・リ−ド・オンリ−・メモリ

Also Published As

Publication number Publication date
JPS63211195A (ja) 1988-09-02
EP0281868A2 (de) 1988-09-14
JPH0632213B2 (ja) 1994-04-27
EP0281868A3 (en) 1990-09-26
US4875194A (en) 1989-10-17
EP0281868B1 (de) 1994-01-19
DE3887180T2 (de) 1994-05-05

Similar Documents

Publication Publication Date Title
DE3576433D1 (de) Halbleiterspeichervorrichtung.
DE3581773D1 (de) Halbleiterspeichervorrichtung.
DE3584189D1 (de) Halbleiterspeichergeraet.
DE3886114D1 (de) Halbleiterspeichergerät mit redundanter Speicherzellenmatrix.
DE3684509D1 (de) Halbleiterspeichergeraet.
DE3681082D1 (de) Halbleiterspeichervorrichtung.
DE3685361D1 (de) Halbleiterspeichervorrichtung.
NL191814C (nl) Halfgeleidergeheugeninrichting.
DE3889097D1 (de) Halbleiterspeicheranordnung.
DE68923505D1 (de) Halbleiterspeicheranordnung.
DE3875767D1 (de) Halbleiter-festwertspeichereinrichtung.
DE3585733D1 (de) Halbleiterspeichereinrichtung mit lese-aenderung-schreib-konfiguration.
DE3887224D1 (de) Halbleiterspeicheranordnung.
DE3578989D1 (de) Halbleiterspeichergeraet mit schreibepruefoperation.
DE3671124D1 (de) Halbleiterspeicherzelle.
DE68918367D1 (de) Halbleiterspeicheranordnung.
DE3767579D1 (de) Nichtfluechtige halbleiter-speichereinrichtung.
DE3884022D1 (de) Halbleiterspeicheranordnung.
DE3785469D1 (de) Halbleiterspeichergeraet mit redundanter speicherzelle.
DE68920946D1 (de) Halbleiter-Speichereinrichtung.
DE3587592D1 (de) Halbleiterspeicheranordnung mit Leseverstärkern.
DE3889872D1 (de) Halbleiterspeicheranordnung.
DE68923588D1 (de) Halbleiterspeicheranordnung.
DE68921900D1 (de) Halbleiterspeicheranordnung mit serieller Zugriffsanordnung.
DE3889563D1 (de) Halbleiteranordnung mit Schmelzsicherung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee