DE3886273D1 - Integrierte Halbleiterschaltungsanordnung mit Mehrschicht-Stromversorgungsleitungen. - Google Patents

Integrierte Halbleiterschaltungsanordnung mit Mehrschicht-Stromversorgungsleitungen.

Info

Publication number
DE3886273D1
DE3886273D1 DE88109699T DE3886273T DE3886273D1 DE 3886273 D1 DE3886273 D1 DE 3886273D1 DE 88109699 T DE88109699 T DE 88109699T DE 3886273 T DE3886273 T DE 3886273T DE 3886273 D1 DE3886273 D1 DE 3886273D1
Authority
DE
Germany
Prior art keywords
power supply
circuit arrangement
supply lines
semiconductor circuit
integrated semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE88109699T
Other languages
English (en)
Inventor
Hiromasa Takahashi
Kazuyuki Kawauchi
Shigeru Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3886273D1 publication Critical patent/DE3886273D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE88109699T 1987-06-19 1988-06-16 Integrierte Halbleiterschaltungsanordnung mit Mehrschicht-Stromversorgungsleitungen. Expired - Lifetime DE3886273D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62154009A JP2606845B2 (ja) 1987-06-19 1987-06-19 半導体集積回路

Publications (1)

Publication Number Publication Date
DE3886273D1 true DE3886273D1 (de) 1994-01-27

Family

ID=15574914

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88109699T Expired - Lifetime DE3886273D1 (de) 1987-06-19 1988-06-16 Integrierte Halbleiterschaltungsanordnung mit Mehrschicht-Stromversorgungsleitungen.

Country Status (5)

Country Link
US (1) US4989062A (de)
EP (1) EP0295707B1 (de)
JP (1) JP2606845B2 (de)
KR (1) KR910007018B1 (de)
DE (1) DE3886273D1 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2739958B2 (ja) * 1988-06-28 1998-04-15 株式会社東芝 スタンダードセル
US5136355A (en) * 1987-11-25 1992-08-04 Marconi Electronic Devices Limited Interconnecting layer on a semiconductor substrate
JP2668981B2 (ja) * 1988-09-19 1997-10-27 富士通株式会社 半導体集積回路
JP2585799B2 (ja) * 1989-06-30 1997-02-26 株式会社東芝 半導体メモリ装置及びそのバーンイン方法
JP3031966B2 (ja) * 1990-07-02 2000-04-10 株式会社東芝 集積回路装置
JP2580065B2 (ja) * 1990-07-17 1997-02-12 株式会社日立製作所 大規模集積回路の電源配線方法
US5378925A (en) * 1990-07-23 1995-01-03 Seiko Epson Corporation Routing method and arrangement for power lines and signal lines in a microelectronic device
US5117389A (en) * 1990-09-05 1992-05-26 Macronix International Co., Ltd. Flat-cell read-only-memory integrated circuit
JPH04132252A (ja) * 1990-09-21 1992-05-06 Hitachi Ltd 半導体集積回路装置
JPH04159751A (ja) * 1990-10-23 1992-06-02 Mitsubishi Electric Corp 半導体集積回路装置およびその配線方法
KR940003410B1 (ko) * 1991-08-01 1994-04-21 삼성전자 주식회사 망사 구조의 전원선을 가지는 반도체 메모리 장치
US5343058A (en) * 1991-11-18 1994-08-30 Vlsi Technology, Inc. Gate array bases with flexible routing
JP2822781B2 (ja) * 1992-06-11 1998-11-11 三菱電機株式会社 マスタスライス方式半導体集積回路装置
US5508938A (en) * 1992-08-13 1996-04-16 Fujitsu Limited Special interconnect layer employing offset trace layout for advanced multi-chip module packages
US5440506A (en) * 1992-08-14 1995-08-08 Harris Corporation Semiconductor ROM device and method
JP2826446B2 (ja) * 1992-12-18 1998-11-18 三菱電機株式会社 半導体集積回路装置及びその設計方法
JPH06326193A (ja) * 1993-05-11 1994-11-25 Nec Ic Microcomput Syst Ltd 半導体集積回路
US5671397A (en) 1993-12-27 1997-09-23 At&T Global Information Solutions Company Sea-of-cells array of transistors
US6675361B1 (en) * 1993-12-27 2004-01-06 Hyundai Electronics America Method of constructing an integrated circuit comprising an embedded macro
JPH0851159A (ja) * 1994-08-05 1996-02-20 Mitsubishi Electric Corp 半導体集積回路
JPH08330434A (ja) * 1994-12-09 1996-12-13 Mitsubishi Electric Corp 半導体集積回路装置およびその配置配線方法並びにレイアウト方法
US5663677A (en) * 1995-03-30 1997-09-02 Lucent Technologies Inc. Integrated circuit multi-level interconnection technique
JP3948790B2 (ja) * 1997-07-18 2007-07-25 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
JP3522144B2 (ja) * 1999-02-25 2004-04-26 富士通株式会社 容量回路および半導体集積回路装置
JP3390408B2 (ja) * 2000-05-29 2003-03-24 エヌイーシーマイクロシステム株式会社 半導体集積回路
US6462977B2 (en) 2000-08-17 2002-10-08 David Earl Butz Data storage device having virtual columns and addressing layers
US7283381B2 (en) 2000-08-17 2007-10-16 David Earl Butz System and methods for addressing a matrix incorporating virtual columns and addressing layers
JP4497791B2 (ja) * 2002-05-09 2010-07-07 株式会社ルネサステクノロジ 半導体集積回路
EP1369922B1 (de) * 2002-06-07 2011-03-09 STMicroelectronics Srl Mehrschichtige Metallstruktur eines Spannungsversorgungsringes mit großem parasitärem Widerstand
US6944552B2 (en) * 2003-06-25 2005-09-13 Hewlett-Packard Development Company, L.P. System and method for detecting power deficiencies in a computer component
KR101216377B1 (ko) * 2004-12-06 2012-12-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR101064381B1 (ko) * 2009-07-29 2011-09-14 삼성모바일디스플레이주식회사 유기전계발광 표시장치
CN107112280B (zh) * 2014-10-24 2020-08-04 株式会社索思未来 半导体集成电路装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
JPS6074455A (ja) * 1983-09-29 1985-04-26 Fujitsu Ltd マスタスライス集積回路
JPS60192359A (ja) * 1984-03-14 1985-09-30 Nec Corp 半導体メモリ装置
JPS60206161A (ja) * 1984-03-30 1985-10-17 Toshiba Corp 半導体集積回路
JPS61156751A (ja) * 1984-12-28 1986-07-16 Fujitsu Ltd 半導体集積回路
DE3586385T2 (de) * 1984-10-03 1993-01-07 Fujitsu Ltd Integrierte gate-matrixstruktur.
US4774559A (en) * 1984-12-03 1988-09-27 International Business Machines Corporation Integrated circuit chip structure wiring and circuitry for driving highly capacitive on chip wiring nets
JPS6312161A (ja) * 1986-07-03 1988-01-19 Olympus Optical Co Ltd 半導体撮像装置

Also Published As

Publication number Publication date
KR890001179A (ko) 1989-03-18
KR910007018B1 (ko) 1991-09-14
JP2606845B2 (ja) 1997-05-07
EP0295707A2 (de) 1988-12-21
JPS63318144A (ja) 1988-12-27
EP0295707B1 (de) 1993-12-15
US4989062A (en) 1991-01-29
EP0295707A3 (en) 1989-03-29

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Legal Events

Date Code Title Description
8332 No legal effect for de