DE3884633D1 - Verfahren zum Herstellen integrierter Halbleiterschaltungen mit doppelimplantierter Dotierung. - Google Patents

Verfahren zum Herstellen integrierter Halbleiterschaltungen mit doppelimplantierter Dotierung.

Info

Publication number
DE3884633D1
DE3884633D1 DE88100447T DE3884633T DE3884633D1 DE 3884633 D1 DE3884633 D1 DE 3884633D1 DE 88100447 T DE88100447 T DE 88100447T DE 3884633 T DE3884633 T DE 3884633T DE 3884633 D1 DE3884633 D1 DE 3884633D1
Authority
DE
Germany
Prior art keywords
double
integrated semiconductor
semiconductor circuits
producing integrated
implanted doping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE88100447T
Other languages
English (en)
Inventor
Peter J Zdebel
Raymond J Balda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE3884633D1 publication Critical patent/DE3884633D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
DE88100447T 1987-01-30 1988-01-14 Verfahren zum Herstellen integrierter Halbleiterschaltungen mit doppelimplantierter Dotierung. Expired - Lifetime DE3884633D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/008,991 US4740478A (en) 1987-01-30 1987-01-30 Integrated circuit method using double implant doping

Publications (1)

Publication Number Publication Date
DE3884633D1 true DE3884633D1 (de) 1993-11-11

Family

ID=21734916

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88100447T Expired - Lifetime DE3884633D1 (de) 1987-01-30 1988-01-14 Verfahren zum Herstellen integrierter Halbleiterschaltungen mit doppelimplantierter Dotierung.

Country Status (5)

Country Link
US (1) US4740478A (de)
EP (1) EP0276694B1 (de)
JP (1) JP2651915B2 (de)
KR (1) KR960008502B1 (de)
DE (1) DE3884633D1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4772566A (en) * 1987-07-01 1988-09-20 Motorola Inc. Single tub transistor means and method
GB2255226B (en) * 1991-04-23 1995-03-01 Intel Corp Bicmos process for counter doped collector
US5629547A (en) * 1991-04-23 1997-05-13 Intel Corporation BICMOS process for counter doped collector
US5244821A (en) * 1991-06-07 1993-09-14 At&T Bell Laboratories Bipolar fabrication method
KR100292851B1 (ko) * 1991-09-27 2001-09-17 스콧 티. 마이쿠엔 높은얼리전압,고주파성능및고항복전압특성을구비한상보형바이폴라트랜지스터및그제조방법
US5557131A (en) * 1992-10-19 1996-09-17 At&T Global Information Solutions Company Elevated emitter for double poly BICMOS devices
US5932922A (en) * 1994-08-08 1999-08-03 Semicoa Semiconductors Uniform current density and high current gain bipolar transistor
SE511816C3 (sv) 1996-06-17 2000-01-24 Ericsson Telefon Ab L M Resistor innefattande en resistorkropp av polykristallint kisel samt foerfarande foer framstaellning av en saadan
US7300850B2 (en) * 2005-09-30 2007-11-27 Semiconductor Components Industries, L.L.C. Method of forming a self-aligned transistor

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US30282A (en) * 1860-10-09 Quartz crusher and amalgamator
US4381953A (en) * 1980-03-24 1983-05-03 International Business Machines Corporation Polysilicon-base self-aligned bipolar transistor process
US4319932A (en) * 1980-03-24 1982-03-16 International Business Machines Corporation Method of making high performance bipolar transistor with polysilicon base contacts
US4608589A (en) * 1980-07-08 1986-08-26 International Business Machines Corporation Self-aligned metal structure for integrated circuits
US4545113A (en) * 1980-10-23 1985-10-08 Fairchild Camera & Instrument Corporation Process for fabricating a lateral transistor having self-aligned base and base contact
US4385946A (en) * 1981-06-19 1983-05-31 Bell Telephone Laboratories, Incorporated Rapid alteration of ion implant dopant species to create regions of opposite conductivity
US4483726A (en) * 1981-06-30 1984-11-20 International Business Machines Corporation Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area
EP0071665B1 (de) * 1981-08-08 1986-04-16 Deutsche ITT Industries GmbH Verfahren zum Herstellen einer monolithisch integrierten Festkörperschaltung mit mindestens einem bipolaren Planartransistor
JPS5866359A (ja) * 1981-09-28 1983-04-20 Fujitsu Ltd 半導体装置の製造方法
JPS5893347A (ja) * 1981-11-30 1983-06-03 Toshiba Corp Ｍｏｓ型半導体装置及びその製造方法
JPS58132946A (ja) * 1982-02-03 1983-08-08 Toshiba Corp 半導体装置の製造方法
US4593453A (en) * 1982-06-01 1986-06-10 Rockwell International Corporation Two-level transistor structures and method utilizing minimal area therefor
US4456489A (en) * 1982-10-15 1984-06-26 Motorola, Inc. Method of forming a shallow and high conductivity boron doped layer in silicon
GB8300617D0 (en) * 1983-01-11 1983-02-09 Emi Ltd Junction field effect transistor
EP0133339A3 (de) * 1983-07-29 1985-03-20 Trw Inc. Silicid-Bipolartransistor und Verfahren zum Herstellen dieses Transistors
DE3330895A1 (de) * 1983-08-26 1985-03-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von bipolartransistorstrukturen mit selbstjustierten emitter- und basisbereichen fuer hoechstfrequenzschaltungen
JPS6063961A (ja) * 1983-08-30 1985-04-12 Fujitsu Ltd 半導体装置の製造方法
JPS60175453A (ja) * 1984-02-20 1985-09-09 Matsushita Electronics Corp トランジスタの製造方法
US4612701A (en) * 1984-03-12 1986-09-23 Harris Corporation Method to reduce the height of the bird's head in oxide isolated processes
JPS61127174A (ja) * 1984-11-26 1986-06-14 Toshiba Corp 半導体装置の製造方法
US4648909A (en) * 1984-11-28 1987-03-10 Fairchild Semiconductor Corporation Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits
US4604789A (en) * 1985-01-31 1986-08-12 Inmos Corporation Process for fabricating polysilicon resistor in polycide line
US4602421A (en) * 1985-04-24 1986-07-29 The United States Of America As Represented By The Secretary Of The Air Force Low noise polycrystalline semiconductor resistors by hydrogen passivation
US4611384A (en) * 1985-04-30 1986-09-16 Gte Laboratories Incorporated Method of making junction field effect transistor of static induction type
US4669179A (en) * 1985-11-01 1987-06-02 Advanced Micro Devices, Inc. Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions

Also Published As

Publication number Publication date
JP2651915B2 (ja) 1997-09-10
KR880009423A (ko) 1988-09-15
JPS63221670A (ja) 1988-09-14
EP0276694A3 (en) 1989-01-25
US4740478A (en) 1988-04-26
KR960008502B1 (ko) 1996-06-26
EP0276694A2 (de) 1988-08-03
EP0276694B1 (de) 1993-10-06

Similar Documents

Publication Publication Date Title
DE3883792D1 (de) Verfahren zum Herstellen integrierter Halbleiterschaltungen mit polykristallinen Schichten und Kontakten.
DE3881004D1 (de) Verfahren zum herstellen von integrierten cmos-anordnungen mit verringerten gate-laengen.
DE3861889D1 (de) Verfahren zum herstellen von loechern in integrierten halbleiterschaltungen.
DE3381509D1 (de) Verfahren zum herstellen von halbleiteranordnungen.
DE3779672T2 (de) Verfahren zum herstellen einer monokristallinen halbleiterschicht.
DE3786914D1 (de) Verfahren zum herstellen einer integrierten schaltungspackungsstruktur.
DE3575241D1 (de) Halbleiteranordnung und verfahren zum herstellen derselben.
DE3780369T2 (de) Verfahren zum herstellen einer halbleiterstruktur.
DE3685970T2 (de) Verfahren zum herstellen eines halbleiterbauelements.
DE3780923T2 (de) Verfahren zum herstellen von gegenstaenden mit hohem siliziumgehalt und dadurch hergestellte gegenstaende.
DE3483531D1 (de) Verfahren zum herstellen einer integrierten halbleiterschaltkreisanordnung mit einem misfet.
DE3783405D1 (de) Halbleiteranordnung mit einer duennschicht-verdrahtung und verfahren zum herstellen derselben.
DE3684676D1 (de) Verfahren zum herstellen von halbleitersubstraten.
DE3888937T2 (de) Verfahren zum Herstellen von integrierten Schaltungen mit FET.
DE68907782D1 (de) Verfahren zum herstellen von grossen halbleiterschaltungen.
DE3671583D1 (de) Verfahren zum herstellen eines halbleiter-speicherbauelementes.
DE68918306D1 (de) Verfahren zum Herstellen einer integrierten optoelektronischen Schaltung.
DE3886341D1 (de) Halbleiteranordnung mit Höckerelektrode und Verfahren zum Herstellen derselben.
DE3772490D1 (de) Halbleiteranordnung sowie verfahren zum herstellen und testen derselben.
DE68906034D1 (de) Verfahren zum herstellen einer halbleiteranordnung.
DE3784605D1 (de) Verfahren zum herstellen einer halbleitervorrichtung und halbleitervorrichtung.
DE3578266D1 (de) Verfahren zum herstellen von halbleiteranordnungen und dadurch hergestellte anordnungen.
DE3877282T2 (de) Verfahren zum herstellen einer halbleiter-vorrichtung.
DE68914572T2 (de) Verfahren zum Herstellen von Halbleitervorrichtungen.
DE3884633D1 (de) Verfahren zum Herstellen integrierter Halbleiterschaltungen mit doppelimplantierter Dotierung.

Legal Events

Date Code Title Description
8332 No legal effect for de