DE3786967D1 - Protokoll zum ungueltigerklaeren eines cachespeichers fuer ein digitales datenverarbeitungssystem. - Google Patents

Protokoll zum ungueltigerklaeren eines cachespeichers fuer ein digitales datenverarbeitungssystem.

Info

Publication number
DE3786967D1
DE3786967D1 DE8787402052T DE3786967T DE3786967D1 DE 3786967 D1 DE3786967 D1 DE 3786967D1 DE 8787402052 T DE8787402052 T DE 8787402052T DE 3786967 T DE3786967 T DE 3786967T DE 3786967 D1 DE3786967 D1 DE 3786967D1
Authority
DE
Germany
Prior art keywords
cache
invalidate
protocol
data processing
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787402052T
Other languages
English (en)
Other versions
DE3786967T2 (de
Inventor
Paul Rubinfeld
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE3786967D1 publication Critical patent/DE3786967D1/de
Application granted granted Critical
Publication of DE3786967T2 publication Critical patent/DE3786967T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
DE87402052T 1986-09-18 1987-09-15 Protokoll zum Ungültigerklären eines Cachespeichers für ein digitales Datenverarbeitungssystem. Expired - Fee Related DE3786967T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/908,825 US4814981A (en) 1986-09-18 1986-09-18 Cache invalidate protocol for digital data processing system

Publications (2)

Publication Number Publication Date
DE3786967D1 true DE3786967D1 (de) 1993-09-16
DE3786967T2 DE3786967T2 (de) 1994-01-13

Family

ID=25426287

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87402052T Expired - Fee Related DE3786967T2 (de) 1986-09-18 1987-09-15 Protokoll zum Ungültigerklären eines Cachespeichers für ein digitales Datenverarbeitungssystem.

Country Status (10)

Country Link
US (1) US4814981A (de)
EP (1) EP0261029B1 (de)
JP (1) JPH0640317B2 (de)
CN (2) CN1010619B (de)
AT (1) ATE93074T1 (de)
AU (1) AU603601B2 (de)
BR (1) BR8705181A (de)
CA (1) CA1296106C (de)
DE (1) DE3786967T2 (de)
IE (1) IE872521L (de)

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US6601189B1 (en) 1999-10-01 2003-07-29 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6349371B1 (en) 1999-10-01 2002-02-19 Stmicroelectronics Ltd. Circuit for storing information
US6633971B2 (en) 1999-10-01 2003-10-14 Hitachi, Ltd. Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline
US6918065B1 (en) 1999-10-01 2005-07-12 Hitachi, Ltd. Method for compressing and decompressing trace information
US6826191B1 (en) 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US6567932B2 (en) 1999-10-01 2003-05-20 Stmicroelectronics Limited System and method for communicating with an integrated circuit
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US6629207B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method for loading instructions or data into a locked way of a cache memory
US6859891B2 (en) 1999-10-01 2005-02-22 Stmicroelectronics Limited Apparatus and method for shadowing processor information
US6701405B1 (en) 1999-10-01 2004-03-02 Hitachi, Ltd. DMA handshake protocol
US6546480B1 (en) 1999-10-01 2003-04-08 Hitachi, Ltd. Instructions for arithmetic operations on vectored data
US6629115B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method and apparatus for manipulating vectored data
US7260745B1 (en) 1999-10-01 2007-08-21 Stmicroelectronics Ltd. Detection of information on an interconnect
US6779145B1 (en) 1999-10-01 2004-08-17 Stmicroelectronics Limited System and method for communicating with an integrated circuit
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US6457118B1 (en) 1999-10-01 2002-09-24 Hitachi Ltd Method and system for selecting and using source operands in computer system instructions
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US7000078B1 (en) 1999-10-01 2006-02-14 Stmicroelectronics Ltd. System and method for maintaining cache coherency in a shared memory system
US6542983B1 (en) 1999-10-01 2003-04-01 Hitachi, Ltd. Microcomputer/floating point processor interface and method
US6615370B1 (en) 1999-10-01 2003-09-02 Hitachi, Ltd. Circuit for storing trace information
US6463553B1 (en) 1999-10-01 2002-10-08 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US6412047B2 (en) 1999-10-01 2002-06-25 Stmicroelectronics, Inc. Coherency protocol
US6502210B1 (en) 1999-10-01 2002-12-31 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US6434665B1 (en) 1999-10-01 2002-08-13 Stmicroelectronics, Inc. Cache memory store buffer
US6574651B1 (en) 1999-10-01 2003-06-03 Hitachi, Ltd. Method and apparatus for arithmetic operation on vectored data
US7072817B1 (en) 1999-10-01 2006-07-04 Stmicroelectronics Ltd. Method of designing an initiator in an integrated circuit
US6298394B1 (en) 1999-10-01 2001-10-02 Stmicroelectronics, Ltd. System and method for capturing information on an interconnect in an integrated circuit
US6598128B1 (en) 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6449712B1 (en) 1999-10-01 2002-09-10 Hitachi, Ltd. Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions
US7310706B1 (en) * 2001-06-01 2007-12-18 Mips Technologies, Inc. Random cache line refill
US8799429B1 (en) * 2008-05-06 2014-08-05 American Megatrends, Inc. Boot acceleration by consolidating client-specific boot data in a data storage system
US9009413B2 (en) * 2012-12-21 2015-04-14 Intel Corporation Method and apparatus to implement lazy flush in a virtually tagged cache memory
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US11157409B2 (en) 2019-12-17 2021-10-26 International Business Machines Corporation Cache snooping mode extending coherence protection for certain requests
US11157408B2 (en) 2019-12-17 2021-10-26 International Business Machines Corporation Cache snooping mode extending coherence protection for certain requests

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Also Published As

Publication number Publication date
CN1048459A (zh) 1991-01-09
JPS63163940A (ja) 1988-07-07
US4814981A (en) 1989-03-21
CN1019236B (zh) 1992-11-25
AU7793687A (en) 1988-03-24
BR8705181A (pt) 1988-05-24
EP0261029A2 (de) 1988-03-23
JPH0640317B2 (ja) 1994-05-25
CN87106353A (zh) 1988-06-08
CA1296106C (en) 1992-02-18
EP0261029A3 (en) 1990-05-23
DE3786967T2 (de) 1994-01-13
CN1010619B (zh) 1990-11-28
EP0261029B1 (de) 1993-08-11
ATE93074T1 (de) 1993-08-15
AU603601B2 (en) 1990-11-22
IE872521L (en) 1988-03-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee