ES8606690A1 - Un aparato de control de acceso a memoria,de aplicaciones electronicas - Google Patents

Un aparato de control de acceso a memoria,de aplicaciones electronicas

Info

Publication number
ES8606690A1
ES8606690A1 ES540736A ES540736A ES8606690A1 ES 8606690 A1 ES8606690 A1 ES 8606690A1 ES 540736 A ES540736 A ES 540736A ES 540736 A ES540736 A ES 540736A ES 8606690 A1 ES8606690 A1 ES 8606690A1
Authority
ES
Spain
Prior art keywords
address
circuit
detecting
real address
image data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES540736A
Other languages
English (en)
Other versions
ES540736A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES540736A0 publication Critical patent/ES540736A0/es
Publication of ES8606690A1 publication Critical patent/ES8606690A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/12—Digital output to print unit, e.g. line printer, chain printer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management

Abstract

UN APARATO DE CONTROL DE ACCERO A MEMORIA. COMPRENDE UN CIRCUITO DETECTOR DE DIRECCIONES PARA DETECTAR UNA DIRECCION REAL EN LA CUAL HAN SIDO ALMACENADOS DATOS DE LECTURA, UN CIRCUITO DE ALMACENAMIENTO DE CORRESPONDENCIA PARA ALMACENAR INFORMACION DE CORRESPONDENCIA ENTRE UNA DIRECCION REAL Y UNA DIRECCION LOGICA, Y UN CIRCUITO DE CONTROL PARA CONTROLAR UNA OPERACION DE INSCRIPCION DE TAL MODO QUE, EN UNA DIRECCION REAL DE LECTURA DETECTADA POR DICHO CIRCUITO DETECTOR DE DIRECCIONES, SE INSCRIBE UNA UNIDAD DE TRANSFERENCIA DE DATOS ALMACENADA ANTERIORMENTE EN LA DIRECCION REAL DE LECTURA, ESPECIFICANDO LA DIRECCION LOGICA CORRESPONDIENTE, CON LO CUAL PUEDE EFECTUARSE UNA LECTURA CONTINUA SIN NINGUNA INTERRUPCION DEBIDA A UNA OPERACION DE INSCRIPCION.
ES540736A 1984-02-29 1985-02-27 Un aparato de control de acceso a memoria,de aplicaciones electronicas Expired ES8606690A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59037883A JPS60181942A (ja) 1984-02-29 1984-02-29 メモリ制御装置

Publications (2)

Publication Number Publication Date
ES540736A0 ES540736A0 (es) 1986-04-01
ES8606690A1 true ES8606690A1 (es) 1986-04-01

Family

ID=12509935

Family Applications (1)

Application Number Title Priority Date Filing Date
ES540736A Expired ES8606690A1 (es) 1984-02-29 1985-02-27 Un aparato de control de acceso a memoria,de aplicaciones electronicas

Country Status (8)

Country Link
US (1) US4890226A (es)
EP (1) EP0153877B1 (es)
JP (1) JPS60181942A (es)
KR (1) KR900004018B1 (es)
AU (1) AU551648B2 (es)
CA (1) CA1231463A (es)
DE (1) DE3587375T2 (es)
ES (1) ES8606690A1 (es)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4942541A (en) * 1988-01-22 1990-07-17 Oms, Inc. Patchification system
EP0310228B1 (en) * 1987-07-31 1994-12-14 QMS, Inc. Page printing system using a virtual memory
NL8800158A (nl) * 1988-01-25 1989-08-16 Philips Nv Computersysteem voorzien van een hierarchisch georganiseerd geheugen.
EP0334102B1 (en) * 1988-03-09 1994-11-30 Oki Electric Industry Company, Limited Printing apparatus
US5237645A (en) * 1988-03-09 1993-08-17 Oki America Industry Co., Ltd. Printing apparatus
FR2633744B1 (fr) * 1988-07-01 1991-02-08 Dassault Electronique Dispositif de memoire vive electronique
FR2633745A1 (fr) * 1988-07-01 1990-01-05 Dassault Electronique Dispositif d'interface electronique entre une memoire partagee et une pluralite d'utilisateurs
JPH02117243A (ja) * 1988-10-27 1990-05-01 Toshiba Corp パケット通信装置
EP0374338B1 (en) * 1988-12-23 1995-02-22 International Business Machines Corporation Shared intelligent memory for the interconnection of distributed micro processors
JP2575208B2 (ja) * 1989-04-20 1997-01-22 沖電気工業株式会社 印刷装置
JPH0373037A (ja) * 1989-05-26 1991-03-28 Hitachi Ltd データベース障害回復方法
US5315708A (en) * 1990-02-28 1994-05-24 Micro Technology, Inc. Method and apparatus for transferring data through a staging memory
JP2989665B2 (ja) * 1990-02-28 1999-12-13 イーエムシー コーポレーション ステージングメモリを介してデータを転送する方法および装置
US5517641A (en) * 1992-05-27 1996-05-14 Cdb Software, Inc. Restartable method to reorganize DB2 tablespace records by determining new physical positions for the records prior to moving using a non sorting technic
US5408654A (en) * 1992-05-27 1995-04-18 Cdb Software, Inc. Method to reorganize an index file without sorting by changing the physical order of pages to match the logical order determined from the index structure
US5511152A (en) * 1993-09-20 1996-04-23 Digital Equipment Corporation Memory subsystem for bitmap printer data controller
TW276317B (es) * 1993-12-17 1996-05-21 Hitachi Seisakusyo Kk
US5717918A (en) * 1994-06-17 1998-02-10 Hitachi, Ltd. Method for concurrently performing a physical sequential scan of a database into a database buffer which is queued until a preceding scan is completed
US6076026A (en) * 1997-09-30 2000-06-13 Motorola, Inc. Method and device for vehicle control events data recording and securing
US6032238A (en) * 1998-02-06 2000-02-29 Interantional Business Machines Corporation Overlapped DMA line transfers
US7336380B2 (en) 2001-02-13 2008-02-26 Heidelberger Druckmaschinen Ag Raster generation system and method of processing raster data
JP6238510B2 (ja) * 2012-07-27 2017-11-29 キヤノン株式会社 バッファ、バッファの制御方法、同期制御装置、同期制御方法、画像処理装置および画像処理方法
US11693800B2 (en) * 2020-07-13 2023-07-04 EMC IP Holding Company LLC Managing IO path bandwidth

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728684A (en) * 1970-08-05 1973-04-17 Honeywell Inc Dynamic scanning algorithm for a buffered printer
SE397014B (sv) * 1976-01-20 1977-10-10 Asea Ab Teckengenerator
US4074254A (en) * 1976-07-22 1978-02-14 International Business Machines Corporation Xy addressable and updateable compressed video refresh buffer for digital tv display
US4126894A (en) * 1977-02-17 1978-11-21 Xerox Corporation Memory overlay linking system
AU523670B2 (en) * 1977-12-08 1982-08-12 Honeywell Information Systems Incorp. Cache memory location selection mechanism
US4153950A (en) * 1978-07-21 1979-05-08 International Business Machines Corp. Data bit assembler
US4203107A (en) * 1978-11-08 1980-05-13 Zentec Corporation Microcomputer terminal system having a list mode operation for the video refresh circuit
JPS5672751A (en) * 1979-11-20 1981-06-17 Fujitsu Ltd Data transfer buffer unit
JPS5829186A (ja) * 1981-08-14 1983-02-21 Nec Corp 情報処理装置
JPS584470A (ja) * 1981-07-01 1983-01-11 Hitachi Ltd メモリ制御装置
US4570217A (en) * 1982-03-29 1986-02-11 Allen Bruce S Man machine interface
EP0095931B1 (en) * 1982-05-31 1991-04-17 Fuji Xerox Co., Ltd. Picture data storage system
DE3381991D1 (de) * 1982-06-28 1990-12-20 Toshiba Kawasaki Kk Bildanzeigesteuereinrichtung.
US4590585A (en) * 1982-08-13 1986-05-20 International Business Machines Character generator for raster printer
JPS5948879A (ja) * 1982-09-10 1984-03-21 Hitachi Ltd 記憶制御方式
US4580134A (en) * 1982-11-16 1986-04-01 Real Time Design, Inc. Color video system using data compression and decompression
US4496976A (en) * 1982-12-27 1985-01-29 Rockwell International Corporation Reduced memory graphics-to-raster scan converter
US4646259A (en) * 1983-11-14 1987-02-24 Minolta Camera Kabushiki Kaisha Strip map memory controller

Also Published As

Publication number Publication date
KR850007128A (ko) 1985-10-30
JPS60181942A (ja) 1985-09-17
ES540736A0 (es) 1986-04-01
EP0153877A2 (en) 1985-09-04
EP0153877B1 (en) 1993-06-02
DE3587375D1 (de) 1993-07-08
US4890226A (en) 1989-12-26
CA1231463A (en) 1988-01-12
AU3913785A (en) 1985-09-19
AU551648B2 (en) 1986-05-08
DE3587375T2 (de) 1993-09-23
KR900004018B1 (ko) 1990-06-09
EP0153877A3 (en) 1989-08-09

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970401