ES8405568A1 - Perfeccionamientos en los sistemas de transmision digitales - Google Patents

Perfeccionamientos en los sistemas de transmision digitales

Info

Publication number
ES8405568A1
ES8405568A1 ES525130A ES525130A ES8405568A1 ES 8405568 A1 ES8405568 A1 ES 8405568A1 ES 525130 A ES525130 A ES 525130A ES 525130 A ES525130 A ES 525130A ES 8405568 A1 ES8405568 A1 ES 8405568A1
Authority
ES
Spain
Prior art keywords
store
aligner
data
read
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES525130A
Other languages
English (en)
Other versions
ES525130A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
British Telecommunications PLC
Original Assignee
British Telecommunications PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Telecommunications PLC filed Critical British Telecommunications PLC
Publication of ES525130A0 publication Critical patent/ES525130A0/es
Publication of ES8405568A1 publication Critical patent/ES8405568A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers

Abstract

PERFECCIONAMIENTOS EN LOS SISTEMAS DE TRANSMISION DIGITALES.COMPRENDE OCHO MEMORIAS INTERMEDIAS (140 A 147). CADA UNA TIENE UNA BARRA (120) DE DISTRIBUCION DE HABLA PARALELA DE OCHO BITS CONECTADA A CONVERTIDORES PARALELOS SERIADOS (121 A 128). T ENE UNA UNIDAD LOGICA ARITMETICA (18) COMUN A TODAS LAS MEMORIAS INTERMEDIAS, PROPORCIONANDO SEÑALES DE CONTROL DE LECTURA (CL) PARA LAS MEMORIAS INTERMEDIAS SOBRE EL HAZ DE CANALES (27). LOS CONVERTIDORES (121 A 128) ESCOGEN CADA OCTAVO BIT DEL HAZ COMUN PARA ACTIVAR LOS HACES DE SALIDA SERIADOS. EL CALCULO DE LA DIRECCIONDE LA MEMORIA SE HA DE REALIZAR EN 488 M/SEG, LO QUE CORRESPONDE A 2 MBITS/SEG. A SON SISTEMAS DE ENTRADA PCM (2 MBITS/SEG); B SON SISTEMAS DE SALIDA PCM; DDE SON DATOS DE LA DIRECCION DE ESCRITURA; EDRT ES LA ENTRADA DE LA DIRECCION DE RANURA DE TIEMPO Y ICM ES LA INTERFAZ DE CONTROL DE MICROPROCESADOR.
ES525130A 1982-08-26 1983-08-24 Perfeccionamientos en los sistemas de transmision digitales Expired ES8405568A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8224481 1982-08-26

Publications (2)

Publication Number Publication Date
ES525130A0 ES525130A0 (es) 1984-06-16
ES8405568A1 true ES8405568A1 (es) 1984-06-16

Family

ID=10532528

Family Applications (1)

Application Number Title Priority Date Filing Date
ES525130A Expired ES8405568A1 (es) 1982-08-26 1983-08-24 Perfeccionamientos en los sistemas de transmision digitales

Country Status (15)

Country Link
US (1) US4535446A (es)
EP (1) EP0102810B1 (es)
JP (1) JPS5989099A (es)
KR (1) KR840005958A (es)
AU (1) AU558405B2 (es)
BR (1) BR8304595A (es)
CA (1) CA1212743A (es)
DE (1) DE3367994D1 (es)
DK (1) DK390683A (es)
ES (1) ES8405568A1 (es)
FI (1) FI833041A (es)
NO (1) NO833046L (es)
NZ (1) NZ205365A (es)
PT (1) PT77252B (es)
ZA (1) ZA836138B (es)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2151437B (en) * 1983-12-13 1987-04-29 Plessey Co Plc Frame aligner for use in telecommunication exchange systems
NL8502023A (nl) * 1985-07-15 1987-02-02 Philips Nv Werkwijze voor het schakelen van tijdsloten in een tdm-signaal en inrichting voor het uitvoeren van de werkwijze.
US4736362A (en) * 1985-07-26 1988-04-05 Advanced Micro Devices, Inc. Programmable data-routing multiplexer
JPH0666766B2 (ja) * 1985-10-11 1994-08-24 日本電気株式会社 フレ−ムアライナ回路
JPS62188444A (ja) * 1986-02-13 1987-08-18 Nec Corp フレ−ム位相同期回路
US4771418A (en) * 1986-07-28 1988-09-13 Advanced Micro Devices, Inc. Time-slot assigner multiplexer
US5081575A (en) * 1987-11-06 1992-01-14 Oryx Corporation Highly parallel computer architecture employing crossbar switch with selectable pipeline delay
CA1311818C (en) * 1987-12-29 1992-12-22 Nec Corporation Time division switching for multi-channel calls using two time switch memories acting as a frame aligner
JP2512786B2 (ja) * 1988-07-18 1996-07-03 富士通株式会社 位相整合回路
US5271006A (en) * 1989-07-19 1993-12-14 Hitachi, Ltd. Frame aligner and method and system for control thereof
CH679818A5 (es) * 1989-10-06 1992-04-15 Alcatel Str Ag
JP2804126B2 (ja) * 1989-11-10 1998-09-24 株式会社日立製作所 フレーム位相変換方法および信号伝送方法
JPH0799831B2 (ja) * 1990-10-08 1995-10-25 株式会社東芝 Ａｔｍ通信システム用単位セルスイッチ
US5416778A (en) * 1992-06-26 1995-05-16 U.S. Philips Corporation Digital radio communication system and primary and secondary station for use in such a system
JPH06261015A (ja) * 1993-01-11 1994-09-16 Mitsubishi Electric Corp フレーム位相同期装置及びフレーム位相同期方法及び時分割多重フレーム位相同期装置
US5515371A (en) * 1994-10-26 1996-05-07 Adtran Timeslot interleaving delay compensation (bonding) mechanism for time division multiplexed digital communication network
DE19722433A1 (de) 1997-05-28 1998-12-03 Siemens Ag Verfahren und Vorrichtung zur Übertragung eines kontinuierlichen Datenstroms in paketierter Form
US6724846B1 (en) * 2000-04-28 2004-04-20 Hewlett-Packard Development Company, L.P. Simple, high performance, bit-sliced mesochronous synchronizer for a source synchronous link

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH501344A (de) * 1969-07-14 1970-12-31 Standard Telephon & Radio Ag Verfahren zur Durchschaltung von PCM-Kanälen in einer zentralgesteuerten elektronischen Fernmelde-Vermittlungsanlage
US3637941A (en) * 1970-07-13 1972-01-25 Gte Automatic Electric Lab Inc Integrated switching and transmission network for pulse code modulated signals
FR2119152A5 (es) * 1970-12-22 1972-08-04 Lannionnais Electronique
US3903371A (en) * 1974-07-01 1975-09-02 Bell Telephone Labor Inc Common control framing detector
JPS5428516A (en) * 1977-08-08 1979-03-03 Nippon Telegr & Teleph Corp <Ntt> Channel converter
US4224474A (en) * 1978-09-28 1980-09-23 Western Geophysical Co. Of America Method and apparatus for demultiplexing multiplexed seismic data
US4312063A (en) * 1979-09-27 1982-01-19 Communications Satellite Corporation TDM Data reorganization apparatus

Also Published As

Publication number Publication date
NO833046L (no) 1984-02-27
PT77252A (en) 1983-09-01
AU558405B2 (en) 1987-01-29
PT77252B (en) 1986-02-12
BR8304595A (pt) 1984-04-03
ZA836138B (en) 1984-04-25
AU1810183A (en) 1984-03-01
EP0102810B1 (en) 1986-11-26
ES525130A0 (es) 1984-06-16
FI833041A (fi) 1984-02-27
CA1212743A (en) 1986-10-14
NZ205365A (en) 1986-03-14
DE3367994D1 (en) 1987-01-15
JPS5989099A (ja) 1984-05-23
DK390683D0 (da) 1983-08-26
DK390683A (da) 1984-02-27
FI833041A0 (fi) 1983-08-25
KR840005958A (ko) 1984-11-19
US4535446A (en) 1985-08-13
EP0102810A1 (en) 1984-03-14

Similar Documents

Publication Publication Date Title
ES8405568A1 (es) Perfeccionamientos en los sistemas de transmision digitales
TW359835B (en) Non-volatile memory enabling simultaneous reading and writing by time multiplexing a decode path
ES8606690A1 (es) Un aparato de control de acceso a memoria,de aplicaciones electronicas
TW330357B (en) Encoding error correction/detection decoder
EP0353610A3 (en) Multiplexing apparatus
EP0365023A3 (en) Address control circuit for data memory employed in signal delay circuit
JPS57196677A (en) Storage device for character graphic information
ES458285A1 (es) Perfeccionamientos en sistemas de proceso de datos.
JP2969896B2 (ja) Ｒａｍのデータ書き込み制御方法
JPS57201000A (en) Bit shift control system of sequential access memory
TW355901B (en) Image signal processing apparatus
JPS5476114A (en) Information signal reproducer
JPS6423488A (en) Memory
SU1222098A1 (ru) Буферное запоминающее устройство
JPS5730172A (en) Buffer memory control system
KR960001749B1 (en) High speed memory access circuit
JPS6482874A (en) Parallel entropy decoding method
JPS6448175A (en) Address control method for picture memory
JPS56156093A (en) Channel memory control system for time-division switchboard
GB1017600A (en) Improvements in or relating to information storage devices
JPS57148462A (en) Original reading and transferring device
JPS6441599A (en) Time switch circuit
JPS6216600B2 (es)
JPS6442728A (en) Writing circuit for magnetic disk device
JPS5736368A (en) Read and control system for hand written signal