ATE93074T1 - Protokoll zum ungueltigerklaeren eines cachespeichers fuer ein digitales datenverarbeitungssystem. - Google Patents

Protokoll zum ungueltigerklaeren eines cachespeichers fuer ein digitales datenverarbeitungssystem.

Info

Publication number
ATE93074T1
ATE93074T1 AT87402052T AT87402052T ATE93074T1 AT E93074 T1 ATE93074 T1 AT E93074T1 AT 87402052 T AT87402052 T AT 87402052T AT 87402052 T AT87402052 T AT 87402052T AT E93074 T1 ATE93074 T1 AT E93074T1
Authority
AT
Austria
Prior art keywords
cache
voiding
protocol
correspondence
contents
Prior art date
Application number
AT87402052T
Other languages
English (en)
Inventor
Paul Rubinfeld
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE93074T1 publication Critical patent/ATE93074T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
AT87402052T 1986-09-18 1987-09-15 Protokoll zum ungueltigerklaeren eines cachespeichers fuer ein digitales datenverarbeitungssystem. ATE93074T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/908,825 US4814981A (en) 1986-09-18 1986-09-18 Cache invalidate protocol for digital data processing system
EP87402052A EP0261029B1 (de) 1986-09-18 1987-09-15 Protokoll zum Ungültigerklären eines Cachespeichers für ein digitales Datenverarbeitungssystem

Publications (1)

Publication Number Publication Date
ATE93074T1 true ATE93074T1 (de) 1993-08-15

Family

ID=25426287

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87402052T ATE93074T1 (de) 1986-09-18 1987-09-15 Protokoll zum ungueltigerklaeren eines cachespeichers fuer ein digitales datenverarbeitungssystem.

Country Status (10)

Country Link
US (1) US4814981A (de)
EP (1) EP0261029B1 (de)
JP (1) JPH0640317B2 (de)
CN (2) CN1010619B (de)
AT (1) ATE93074T1 (de)
AU (1) AU603601B2 (de)
BR (1) BR8705181A (de)
CA (1) CA1296106C (de)
DE (1) DE3786967T2 (de)
IE (1) IE872521L (de)

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Also Published As

Publication number Publication date
US4814981A (en) 1989-03-21
DE3786967T2 (de) 1994-01-13
EP0261029B1 (de) 1993-08-11
CA1296106C (en) 1992-02-18
AU603601B2 (en) 1990-11-22
AU7793687A (en) 1988-03-24
JPH0640317B2 (ja) 1994-05-25
CN1048459A (zh) 1991-01-09
EP0261029A3 (en) 1990-05-23
DE3786967D1 (de) 1993-09-16
JPS63163940A (ja) 1988-07-07
CN1019236B (zh) 1992-11-25
BR8705181A (pt) 1988-05-24
EP0261029A2 (de) 1988-03-23
CN1010619B (zh) 1990-11-28
IE872521L (en) 1988-03-18
CN87106353A (zh) 1988-06-08

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