DE3688410T2 - Verfahren, System und Schaltung zur Anpassung der Verzögerungszeit. - Google Patents
Verfahren, System und Schaltung zur Anpassung der Verzögerungszeit.Info
- Publication number
- DE3688410T2 DE3688410T2 DE19863688410 DE3688410T DE3688410T2 DE 3688410 T2 DE3688410 T2 DE 3688410T2 DE 19863688410 DE19863688410 DE 19863688410 DE 3688410 T DE3688410 T DE 3688410T DE 3688410 T2 DE3688410 T2 DE 3688410T2
- Authority
- DE
- Germany
- Prior art keywords
- signal
- data
- clock
- signals
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
- H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60195623A JPS6256040A (ja) | 1985-09-04 | 1985-09-04 | 遅延時間補償回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE3688410D1 DE3688410D1 (de) | 1993-06-17 |
| DE3688410T2 true DE3688410T2 (de) | 1993-11-11 |
Family
ID=16344247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19863688410 Expired - Fee Related DE3688410T2 (de) | 1985-09-04 | 1986-09-04 | Verfahren, System und Schaltung zur Anpassung der Verzögerungszeit. |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0213641B1 (enExample) |
| JP (1) | JPS6256040A (enExample) |
| DE (1) | DE3688410T2 (enExample) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4811364A (en) * | 1988-04-01 | 1989-03-07 | Digital Equipment Corporation | Method and apparatus for stabilized data transmission |
| US4979190A (en) * | 1988-04-01 | 1990-12-18 | Digital Equipment Corporation | Method and apparatus for stabilized data transmission |
| JPH0435394A (ja) * | 1990-05-28 | 1992-02-06 | Fujitsu Ltd | 高品位テレビ信号符号化装置 |
| JP2816384B2 (ja) * | 1990-06-14 | 1998-10-27 | 富士通株式会社 | 位相補正方法及び回路 |
| US5119402A (en) * | 1990-06-26 | 1992-06-02 | Digital Equipment Corporation | Method and apparatus for transmission of local area network signals over unshielded twisted pairs |
| US5341405A (en) * | 1991-06-11 | 1994-08-23 | Digital Equipment Corporation | Data recovery apparatus and methods |
| US5408473A (en) * | 1992-03-03 | 1995-04-18 | Digital Equipment Corporation | Method and apparatus for transmission of communication signals over two parallel channels |
| JP3345011B2 (ja) * | 1992-07-20 | 2002-11-18 | シーメンス アクチエンゲゼルシヤフト | 通信セルの順序の維持の下に複数の並列接続線路を介して通信セル流を転送する方法 |
| US5359630A (en) * | 1992-08-13 | 1994-10-25 | Digital Equipment Corporation | Method and apparatus for realignment of synchronous data |
| TW419924B (en) * | 1998-02-16 | 2001-01-21 | Nippon Telegraph & Telephone | Channel-to-channel skew compensation |
| EP0996262A1 (en) * | 1998-10-22 | 2000-04-26 | Texas Instruments France | Communication system with plurality of synchronised data links |
| US6963989B1 (en) * | 2000-05-22 | 2005-11-08 | Micron Technology, Inc. | Method and apparatus for adjusting data hold timing of an output circuit |
| US7035368B2 (en) | 2002-03-18 | 2006-04-25 | Texas Instruments Incorporated | High speed parallel link receiver |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB968730A (enExample) * | 1962-02-09 |
-
1985
- 1985-09-04 JP JP60195623A patent/JPS6256040A/ja active Granted
-
1986
- 1986-09-04 EP EP19860112327 patent/EP0213641B1/en not_active Expired - Lifetime
- 1986-09-04 DE DE19863688410 patent/DE3688410T2/de not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0213641B1 (en) | 1993-05-12 |
| JPH035100B2 (enExample) | 1991-01-24 |
| JPS6256040A (ja) | 1987-03-11 |
| EP0213641A2 (en) | 1987-03-11 |
| EP0213641A3 (en) | 1989-05-03 |
| DE3688410D1 (de) | 1993-06-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8339 | Ceased/non-payment of the annual fee |