DE3686603D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3686603D1
DE3686603D1 DE8686108267T DE3686603T DE3686603D1 DE 3686603 D1 DE3686603 D1 DE 3686603D1 DE 8686108267 T DE8686108267 T DE 8686108267T DE 3686603 T DE3686603 T DE 3686603T DE 3686603 D1 DE3686603 D1 DE 3686603D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
arrangement
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686108267T
Other languages
English (en)
Other versions
DE3686603T2 (de
Inventor
Yasunori Tanaka
Hideo Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Tosbac Computer System Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp, Tosbac Computer System Co Ltd filed Critical Toshiba Corp
Publication of DE3686603D1 publication Critical patent/DE3686603D1/de
Application granted granted Critical
Publication of DE3686603T2 publication Critical patent/DE3686603T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B62LAND VEHICLES FOR TRAVELLING OTHERWISE THAN ON RAILS
    • B62LBRAKES SPECIALLY ADAPTED FOR CYCLES
    • B62L3/00Brake-actuating mechanisms; Arrangements thereof
    • B62L3/04Brake-actuating mechanisms; Arrangements thereof for control by a foot lever
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
DE8686108267T 1985-06-18 1986-06-18 Halbleiterspeicheranordnung. Expired - Lifetime DE3686603T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60130867A JPH0783062B2 (ja) 1985-06-18 1985-06-18 マスタ−スライス型半導体装置

Publications (2)

Publication Number Publication Date
DE3686603D1 true DE3686603D1 (de) 1992-10-08
DE3686603T2 DE3686603T2 (de) 1993-03-18

Family

ID=15044552

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686108267T Expired - Lifetime DE3686603T2 (de) 1985-06-18 1986-06-18 Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4873670A (de)
EP (1) EP0206229B1 (de)
JP (1) JPH0783062B2 (de)
KR (1) KR900004326B1 (de)
DE (1) DE3686603T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4899308A (en) * 1986-12-11 1990-02-06 Fairchild Semiconductor Corporation High density ROM in a CMOS gate array
JPH03179780A (ja) * 1989-12-07 1991-08-05 Fujitsu Ltd 半導体装置
US5420818A (en) * 1994-01-03 1995-05-30 Texas Instruments Incorporated Static read only memory (ROM)
JPH10134566A (ja) * 1996-10-31 1998-05-22 Mitsubishi Electric Corp 記憶機能を有する半導体装置及びそのデータ読み出し方法
DE102004056459B4 (de) 2004-11-23 2007-01-18 Infineon Technologies Ag ROM-Speicherzelle mit definierten Bitleitungsspannungen

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648071A (en) * 1970-02-04 1972-03-07 Nat Semiconductor Corp High-speed mos sense amplifier
JPS5947464B2 (ja) * 1974-09-11 1984-11-19 株式会社日立製作所 半導体装置
JPS5736857A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Mos semiconductor device
JPS5878467A (ja) * 1981-11-05 1983-05-12 Seiko Instr & Electronics Ltd 不揮発性半導体メモリ
US4434381A (en) * 1981-12-07 1984-02-28 Rca Corporation Sense amplifiers
JPS592291A (ja) * 1982-06-28 1984-01-07 Fujitsu Ltd プログラマブル・リ−ドオンリ・メモリ装置
US4575823A (en) * 1982-08-17 1986-03-11 Westinghouse Electric Corp. Electrically alterable non-volatile memory
US4541077A (en) * 1982-11-12 1985-09-10 National Semiconductor Corporation Self compensating ROM circuit
JPS59180324A (ja) * 1983-03-31 1984-10-13 Fujitsu Ltd 半導体記憶装置
JPS60147998A (ja) * 1984-01-11 1985-08-05 Toshiba Corp 半導体記憶装置
FR2563651B1 (fr) * 1984-04-27 1986-06-27 Thomson Csf Mat Tel Memoire morte realisee en circuit integre prediffuse
JPS61289598A (ja) * 1985-06-17 1986-12-19 Toshiba Corp 読出専用半導体記憶装置
JPH0766659B2 (ja) * 1986-01-30 1995-07-19 三菱電機株式会社 半導体記憶装置
US4658380A (en) * 1986-02-28 1987-04-14 Ncr Corporation CMOS memory margining control circuit for a nonvolatile memory

Also Published As

Publication number Publication date
US4873670A (en) 1989-10-10
KR870000707A (ko) 1987-02-20
EP0206229B1 (de) 1992-09-02
JPH0783062B2 (ja) 1995-09-06
KR900004326B1 (ko) 1990-06-22
JPS61289646A (ja) 1986-12-19
DE3686603T2 (de) 1993-03-18
EP0206229A3 (en) 1988-04-06
EP0206229A2 (de) 1986-12-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP T

8327 Change in the person/name/address of the patent owner

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP T