DE3679868D1 - Verfahren zur herstellung eines feldeffekttransistors. - Google Patents

Verfahren zur herstellung eines feldeffekttransistors.

Info

Publication number
DE3679868D1
DE3679868D1 DE8686110293T DE3679868T DE3679868D1 DE 3679868 D1 DE3679868 D1 DE 3679868D1 DE 8686110293 T DE8686110293 T DE 8686110293T DE 3679868 T DE3679868 T DE 3679868T DE 3679868 D1 DE3679868 D1 DE 3679868D1
Authority
DE
Germany
Prior art keywords
producing
field effect
effect transistor
transistor
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686110293T
Other languages
German (de)
English (en)
Inventor
Takamoto Enoki
Kimiyoshi Yamasaki
Kuniki Ohwada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Application granted granted Critical
Publication of DE3679868D1 publication Critical patent/DE3679868D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
    • H10D30/0614—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs using processes wherein the final gate is made after the completion of the source and drain regions, e.g. gate-last processes using dummy gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/139—Schottky barrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
DE8686110293T 1985-07-29 1986-07-25 Verfahren zur herstellung eines feldeffekttransistors. Expired - Lifetime DE3679868D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60167304A JPS6229175A (ja) 1985-07-29 1985-07-29 電界効果型トランジスタの製造方法

Publications (1)

Publication Number Publication Date
DE3679868D1 true DE3679868D1 (de) 1991-07-25

Family

ID=15847266

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686110293T Expired - Lifetime DE3679868D1 (de) 1985-07-29 1986-07-25 Verfahren zur herstellung eines feldeffekttransistors.

Country Status (4)

Country Link
US (1) US4694564A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0211353B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS6229175A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3679868D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NZ218499A (en) * 1985-12-10 1990-04-26 Genetic Systems Corp Monoclonal antibodies against pseudomonas aeruginosa, pharmaceutical compositions and detection methods
DE3609274A1 (de) * 1986-03-19 1987-09-24 Siemens Ag Verfahren zur herstellung eines selbstjustiert positionierten metallkontaktes
JPS63155671A (ja) * 1986-12-18 1988-06-28 Nec Corp 半導体装置の製造方法
JPS63229720A (ja) * 1987-03-18 1988-09-26 Nec Corp 化合物半導体装置
FR2613134B1 (fr) * 1987-03-24 1990-03-09 Labo Electronique Physique Dispositif semiconducteur du type transistor a effet de champ
JPH0722448B2 (ja) * 1987-03-31 1995-03-15 株式会社クボタ 水田用作業車
US4808545A (en) * 1987-04-20 1989-02-28 International Business Machines Corporation High speed GaAs MESFET having refractory contacts and a self-aligned cold gate fabrication process
US5229323A (en) * 1987-08-21 1993-07-20 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device with Schottky electrodes
US4792531A (en) * 1987-10-05 1988-12-20 Menlo Industries, Inc. Self-aligned gate process
JPH021136A (ja) * 1987-10-23 1990-01-05 Vitesse Semiconductor Corp ３−ｖ族デバイス用の誘電キャップ
JP2685149B2 (ja) * 1988-04-11 1997-12-03 住友電気工業株式会社 電界効果トランジスタの製造方法
GB2237929A (en) * 1989-10-23 1991-05-15 Philips Electronic Associated A method of manufacturing a semiconductor device
JPH03138938A (ja) * 1989-10-24 1991-06-13 Toshiba Corp 半導体装置の製造方法
US5212117A (en) * 1989-10-24 1993-05-18 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device contact structure using lift
KR940007666B1 (ko) * 1990-12-26 1994-08-22 재단법인 한국전자통신연구소 이중층의 내열성 게이트를 사용한 자기정렬형 GaAs 전계효과 트랜지스터의 제조방법
US5888890A (en) * 1994-08-12 1999-03-30 Lg Semicon Co., Ltd. Method of manufacturing field effect transistor
KR100211070B1 (ko) * 1994-08-19 1999-07-15 아끼구사 나오유끼 반도체 장치 및 그 제조방법
US5824575A (en) * 1994-08-22 1998-10-20 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US5744400A (en) * 1996-05-06 1998-04-28 Accord Semiconductor Equipment Group Apparatus and method for dry milling of non-planar features on a semiconductor surface
RU2131631C1 (ru) * 1997-04-18 1999-06-10 Самсоненко Борис Николаевич Способ изготовления полупроводниковых приборов
US6087208A (en) * 1998-03-31 2000-07-11 Advanced Micro Devices, Inc. Method for increasing gate capacitance by using both high and low dielectric gate material
TW400612B (en) * 1998-10-19 2000-08-01 United Microelectronics Corp The manufacturing method of a transistor
US6673714B2 (en) * 2002-04-25 2004-01-06 Hewlett-Packard Development Company, L.P. Method of fabricating a sub-lithographic sized via
US7045404B2 (en) * 2004-01-16 2006-05-16 Cree, Inc. Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof
RU2349987C1 (ru) * 2007-07-17 2009-03-20 Открытое акционерное общество "ОКБ-Планета" Способ изготовления полевого транзистора с барьером шоттки
KR20100073247A (ko) * 2008-12-23 2010-07-01 한국전자통신연구원 자기정렬 전계 효과 트랜지스터 구조체

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4213840A (en) * 1978-11-13 1980-07-22 Avantek, Inc. Low-resistance, fine-line semiconductor device and the method for its manufacture
US4214966A (en) * 1979-03-20 1980-07-29 Bell Telephone Laboratories, Incorporated Process useful in the fabrication of articles with metallized surfaces
US4325181A (en) * 1980-12-17 1982-04-20 The United States Of America As Represented By The Secretary Of The Navy Simplified fabrication method for high-performance FET
JPS58143577A (ja) * 1982-02-22 1983-08-26 Toshiba Corp 埋め込みゲ−ト電界効果トランジスタの製造方法
US4561169A (en) * 1982-07-30 1985-12-31 Hitachi, Ltd. Method of manufacturing semiconductor device utilizing multilayer mask
DE3230945A1 (de) * 1982-08-20 1984-02-23 Telefunken electronic GmbH, 7100 Heilbronn Verfahren zum herstellen eines feldeffekttransistors
JPS59103355A (ja) * 1982-12-06 1984-06-14 Nec Corp 半導体装置
JPS616871A (ja) * 1984-06-21 1986-01-13 Matsushita Electric Ind Co Ltd 電界効果トランジスタの製造方法

Also Published As

Publication number Publication date
JPH0156539B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-11-30
US4694564A (en) 1987-09-22
EP0211353B1 (en) 1991-06-19
JPS6229175A (ja) 1987-02-07
EP0211353A3 (en) 1987-11-19
EP0211353A2 (en) 1987-02-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BENEDUM, U., DIPL.-CHEM.UNIV.DR.RER.NAT., PAT.-ANW., 81669 MUENCHEN