DE3677543D1 - Ein supergitter enthaltende halbleitervorrichtung. - Google Patents

Ein supergitter enthaltende halbleitervorrichtung.

Info

Publication number
DE3677543D1
DE3677543D1 DE8686103408T DE3677543T DE3677543D1 DE 3677543 D1 DE3677543 D1 DE 3677543D1 DE 8686103408 T DE8686103408 T DE 8686103408T DE 3677543 T DE3677543 T DE 3677543T DE 3677543 D1 DE3677543 D1 DE 3677543D1
Authority
DE
Germany
Prior art keywords
supergitter
semiconductor device
device containing
semiconductor
containing supergitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686103408T
Other languages
English (en)
Inventor
Akira Ishibashi
Yoshifumi Mori
Masao Itabashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE3677543D1 publication Critical patent/DE3677543D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H01L29/155—Comprising only semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7376—Resonant tunnelling transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/056—Gallium arsenide
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/072—Heterojunctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/097—Lattice strain and defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/119—Phosphides of gallium or indium
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/16—Superlattice

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
DE8686103408T 1985-03-15 1986-03-13 Ein supergitter enthaltende halbleitervorrichtung. Expired - Lifetime DE3677543D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60052973A JPS61210679A (ja) 1985-03-15 1985-03-15 半導体装置

Publications (1)

Publication Number Publication Date
DE3677543D1 true DE3677543D1 (de) 1991-03-28

Family

ID=12929834

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686103408T Expired - Lifetime DE3677543D1 (de) 1985-03-15 1986-03-13 Ein supergitter enthaltende halbleitervorrichtung.

Country Status (4)

Country Link
US (2) US4835579A (de)
EP (1) EP0201686B1 (de)
JP (1) JPS61210679A (de)
DE (1) DE3677543D1 (de)

Families Citing this family (156)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS624366A (ja) * 1985-07-01 1987-01-10 Fujitsu Ltd ホツトエレクトロントランジスタ
JPS62166564A (ja) * 1986-01-20 1987-07-23 Agency Of Ind Science & Technol 半導体装置
JPS62211948A (ja) * 1986-03-13 1987-09-17 Fujitsu Ltd ヘテロ接合半導体装置
FR2607628B1 (fr) * 1986-11-27 1989-03-17 Centre Nat Rech Scient Modulateur optique a superreseau
JPS63140570A (ja) * 1986-12-03 1988-06-13 Hitachi Ltd 半導体装置
US5258631A (en) * 1987-01-30 1993-11-02 Hitachi, Ltd. Semiconductor device having a two-dimensional electron gas as an active layer
US4956682A (en) * 1987-04-28 1990-09-11 Matsushita Electric Industrial Co., Ltd. Optoelectronic integrated circuit
FR2620863B1 (fr) * 1987-09-22 1989-12-01 Thomson Csf Dispositif optoelectronique a base de composes iii-v sur substrat silicium
US5381027A (en) * 1988-01-26 1995-01-10 Hitachi, Ltd. Semiconductor device having a heterojunction and a two dimensional gas as an active layer
JPH01238161A (ja) * 1988-03-18 1989-09-22 Fujitsu Ltd 半導体装置及びその製造方法
US4905056A (en) * 1988-09-30 1990-02-27 Berndt Dale F Superlattice precision voltage reference
JPH06101588B2 (ja) * 1989-08-22 1994-12-12 京都大学長 半導体材料
JPH03290975A (ja) * 1990-04-09 1991-12-20 Fujitsu Ltd 縦型半導体装置
US5087948A (en) * 1990-06-25 1992-02-11 Massachusetts Institute Of Technology Disorder-induced narrowband high-speed electronic devices
US5160982A (en) * 1991-07-01 1992-11-03 Motorola, Inc. Phonon suppression in quantum wells
US5161996A (en) * 1991-07-26 1992-11-10 Amp Incorporated Header assembly and alignment assist shroud therefor
US5129831A (en) * 1991-07-26 1992-07-14 Amp Incorporated Right angle header shroud to board polarization and keying system
US5426316A (en) * 1992-12-21 1995-06-20 International Business Machines Corporation Triple heterojunction bipolar transistor
JPH0786184A (ja) * 1993-09-20 1995-03-31 Nec Kansai Ltd 結晶成長方法
US5773334A (en) * 1994-09-26 1998-06-30 Toyota Jidosha Kabushiki Kaisha Method of manufacturing a semiconductor device
US6320212B1 (en) * 1999-09-02 2001-11-20 Hrl Laboratories, Llc. Superlattice fabrication for InAs/GaSb/AISb semiconductor structures
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US7535041B2 (en) * 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
EP1644983B1 (de) * 2003-06-26 2008-10-29 Mears Technologies, Inc. Halbleiterbauelement mit einem mosfet mit bandlücken-angepasstem übergitter
US20060231857A1 (en) * 2003-06-26 2006-10-19 Rj Mears, Llc Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device
US20060267130A1 (en) * 2003-06-26 2006-11-30 Rj Mears, Llc Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US20070063186A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
US20060292765A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a FINFET Including a Superlattice
US7045377B2 (en) * 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7514328B2 (en) * 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US20060220118A1 (en) * 2003-06-26 2006-10-05 Rj Mears, Llc Semiconductor device including a dopant blocking superlattice
US20050279991A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Semiconductor device including a superlattice having at least one group of substantially undoped layers
US20060289049A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
US6958486B2 (en) * 2003-06-26 2005-10-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US20060011905A1 (en) * 2003-06-26 2006-01-19 Rj Mears, Llc Semiconductor device comprising a superlattice dielectric interface layer
US7227174B2 (en) * 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7612366B2 (en) * 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7153763B2 (en) 2003-06-26 2006-12-26 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US7598515B2 (en) * 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7491587B2 (en) * 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7586165B2 (en) * 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US7531850B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7531828B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US20060273299A1 (en) * 2003-06-26 2006-12-07 Rj Mears, Llc Method for making a semiconductor device including a dopant blocking superlattice
US7045813B2 (en) * 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7202494B2 (en) * 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
US20060243964A1 (en) * 2003-06-26 2006-11-02 Rj Mears, Llc Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7033437B2 (en) * 2003-06-26 2006-04-25 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US20050282330A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
US7531829B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7229902B2 (en) * 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US20040266116A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Methods of fabricating semiconductor structures having improved conductivity effective mass
US7446002B2 (en) * 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US20070063185A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Semiconductor device including a front side strained superlattice layer and a back side stress layer
US20040262594A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Semiconductor structures having improved conductivity effective mass and methods for fabricating same
US7586116B2 (en) * 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
NL1023764C2 (nl) 2003-06-27 2004-12-28 Leen Huisman B V Insectwerend schermdoek en scherminrichting.
TWM253058U (en) * 2003-09-05 2004-12-11 Visual Photonics Epitaxy Co Lt Heterogeneous junction dipole transistor structure for adjusting on voltage of base and emitter
DE102004058431B4 (de) * 2003-12-05 2021-02-18 Infineon Technologies Americas Corp. III-Nitrid Halbleitervorrichtung mit Grabenstruktur
US7517702B2 (en) * 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US20070166928A1 (en) * 2005-12-22 2007-07-19 Rj Mears, Llc Method for making an electronic device including a selectively polable superlattice
US7718996B2 (en) * 2006-02-21 2010-05-18 Mears Technologies, Inc. Semiconductor device comprising a lattice matching layer
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7928425B2 (en) * 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US7863066B2 (en) * 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7880161B2 (en) * 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7812339B2 (en) * 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
EP2202784B1 (de) * 2008-12-29 2017-10-25 Imec Herstellungsverfahren für einen Übergang
US9099388B2 (en) * 2011-10-21 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. III-V multi-channel FinFETs
US9406753B2 (en) 2013-11-22 2016-08-02 Atomera Incorporated Semiconductor devices including superlattice depletion layer stack and related methods
US9275996B2 (en) 2013-11-22 2016-03-01 Mears Technologies, Inc. Vertical semiconductor devices including superlattice punch through stop layer and related methods
US9716147B2 (en) 2014-06-09 2017-07-25 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
WO2016187038A1 (en) 2015-05-15 2016-11-24 Atomera Incorporated Semiconductor devices with superlattice and punch-through stop (pts) layers at different depths and related methods
US9721790B2 (en) 2015-06-02 2017-08-01 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9558939B1 (en) 2016-01-15 2017-01-31 Atomera Incorporated Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source
US10109342B2 (en) 2016-05-11 2018-10-23 Atomera Incorporated Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods
US10170604B2 (en) 2016-08-08 2019-01-01 Atomera Incorporated Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers
US10107854B2 (en) 2016-08-17 2018-10-23 Atomera Incorporated Semiconductor device including threshold voltage measurement circuitry
CN110832641B (zh) 2017-05-16 2023-05-30 阿托梅拉公司 包括作为吸收层的超晶格的半导体装置和方法
WO2018231929A1 (en) 2017-06-13 2018-12-20 Atomera Incorporated Semiconductor device with recessed channel array transistor (rcat) including a superlattice and associated methods
US10109479B1 (en) 2017-07-31 2018-10-23 Atomera Incorporated Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice
CN111247640B (zh) 2017-08-18 2023-11-03 阿托梅拉公司 包括与超晶格sti界面相邻的非单晶纵梁的半导体器件和方法
US10608043B2 (en) 2017-12-15 2020-03-31 Atomera Incorporation Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
US10367028B2 (en) 2017-12-15 2019-07-30 Atomera Incorporated CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
US10361243B2 (en) 2017-12-15 2019-07-23 Atomera Incorporated Method for making CMOS image sensor including superlattice to enhance infrared light absorption
US10396223B2 (en) 2017-12-15 2019-08-27 Atomera Incorporated Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk
US10461118B2 (en) 2017-12-15 2019-10-29 Atomera Incorporated Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
US10529757B2 (en) 2017-12-15 2020-01-07 Atomera Incorporated CMOS image sensor including pixels with read circuitry having a superlattice
US10355151B2 (en) 2017-12-15 2019-07-16 Atomera Incorporated CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
US10608027B2 (en) 2017-12-15 2020-03-31 Atomera Incorporated Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
US10304881B1 (en) 2017-12-15 2019-05-28 Atomera Incorporated CMOS image sensor with buried superlattice layer to reduce crosstalk
US10276625B1 (en) 2017-12-15 2019-04-30 Atomera Incorporated CMOS image sensor including superlattice to enhance infrared light absorption
US10529768B2 (en) 2017-12-15 2020-01-07 Atomera Incorporated Method for making CMOS image sensor including pixels with read circuitry having a superlattice
WO2019118840A1 (en) 2017-12-15 2019-06-20 Atomera Incorporated Cmos image sensor including stacked semiconductor chips and readout circuitry including a superlattice and related methods
US10615209B2 (en) 2017-12-15 2020-04-07 Atomera Incorporated CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
EP3762959B1 (de) 2018-03-08 2024-04-10 Atomera Incorporated Halbleiterbauelement mit verbesserten kontaktstrukturen mit einem übergitter und zugehörige verfahren
US10727049B2 (en) 2018-03-09 2020-07-28 Atomera Incorporated Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
WO2019173630A1 (en) 2018-03-09 2019-09-12 Atomera Incorporated Semiconductor device and method including compound semiconductor materials and an impurity and point defect blocking superlattice
US10468245B2 (en) 2018-03-09 2019-11-05 Atomera Incorporated Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
EP3776663A1 (de) 2018-04-12 2021-02-17 Atomera Incorporated Vorrichtung und verfahren zur herstellung eines invertierten t-kanal-feldeffekttransistors (itfet) mit einem übergitter
WO2019199923A1 (en) 2018-04-12 2019-10-17 Atomera Incorporated Semiconductor device and method including vertically integrated optical and electronic devices and comprising a superlattice
US10566191B1 (en) 2018-08-30 2020-02-18 Atomera Incorporated Semiconductor device including superlattice structures with reduced defect densities
US10811498B2 (en) 2018-08-30 2020-10-20 Atomera Incorporated Method for making superlattice structures with reduced defect densities
TWI720587B (zh) 2018-08-30 2021-03-01 美商安托梅拉公司 用於製作具較低缺陷密度超晶格結構之方法及元件
US20200135489A1 (en) 2018-10-31 2020-04-30 Atomera Incorporated Method for making a semiconductor device including a superlattice having nitrogen diffused therein
US10840335B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance
US10847618B2 (en) 2018-11-16 2020-11-24 Atomera Incorporated Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance
US10580866B1 (en) 2018-11-16 2020-03-03 Atomera Incorporated Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
US10854717B2 (en) 2018-11-16 2020-12-01 Atomera Incorporated Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance
EP3871270A1 (de) 2018-11-16 2021-09-01 Atomera Incorporated Finfet mit source- und drain-bereichen mit dotierstoffdiffusionssperrenden übergitterschichten zur reduzierung des kontaktwiderstandes und zugehörige verfahren
US10840336B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods
US10818755B2 (en) 2018-11-16 2020-10-27 Atomera Incorporated Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
CN113228295A (zh) 2018-11-16 2021-08-06 阿托梅拉公司 包括源极/漏极掺杂剂扩散阻挡超晶格以减小接触电阻的半导体器件和相关方法
US10580867B1 (en) 2018-11-16 2020-03-03 Atomera Incorporated FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance
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US11682712B2 (en) 2021-05-26 2023-06-20 Atomera Incorporated Method for making semiconductor device including superlattice with O18 enriched monolayers
US11728385B2 (en) 2021-05-26 2023-08-15 Atomera Incorporated Semiconductor device including superlattice with O18 enriched monolayers
TWI812186B (zh) 2021-05-26 2023-08-11 美商安托梅拉公司 包含具氧１８富集單層之超晶格之半導體元件及相關方法
US11721546B2 (en) 2021-10-28 2023-08-08 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms
US11631584B1 (en) 2021-10-28 2023-04-18 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to define etch stop layer
US20230411491A1 (en) 2022-06-21 2023-12-21 Atomera Incorporated Methods for making semiconductor devices with superlattice and embedded quantum dots
WO2024044076A1 (en) 2022-08-23 2024-02-29 Atomera Incorporated Image sensor devices including a superlattice and related methods

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3626257A (en) * 1969-04-01 1971-12-07 Ibm Semiconductor device with superlattice region
US3893044A (en) * 1973-04-12 1975-07-01 Ibm Laser device having enclosed laser cavity
SE393967B (sv) * 1974-11-29 1977-05-31 Sateko Oy Forfarande och for utforande av stroleggning mellan lagren i ett virkespaket
US4122407A (en) * 1976-04-06 1978-10-24 International Business Machines Corporation Heterostructure junction light emitting or responding or modulating devices
US4261771A (en) * 1979-10-31 1981-04-14 Bell Telephone Laboratories, Incorporated Method of fabricating periodic monolayer semiconductor structures by molecular beam epitaxy
US4511408A (en) * 1982-04-22 1985-04-16 The Board Of Trustees Of The University Of Illinois Semiconductor device fabrication with disordering elements introduced into active region
US4639275A (en) * 1982-04-22 1987-01-27 The Board Of Trustees Of The University Of Illinois Forming disordered layer by controlled diffusion in heterojunction III-V semiconductor
US4675709A (en) * 1982-06-21 1987-06-23 Xerox Corporation Quantized layered structures with adjusted indirect bandgap transitions
US4616241A (en) * 1983-03-22 1986-10-07 The United States Of America As Represented By The United States Department Of Energy Superlattice optical device
NL8301215A (nl) * 1983-04-07 1984-11-01 Philips Nv Halfgeleiderinrichting voor het opwekken van electromagnetische straling.
NL8301745A (nl) * 1983-05-17 1984-12-17 Philips Nv Halfgeleiderinrichting.
US4688068A (en) * 1983-07-08 1987-08-18 The United States Of America As Represented By The Department Of Energy Quantum well multijunction photovoltaic cell
US4599728A (en) * 1983-07-11 1986-07-08 At&T Bell Laboratories Multi-quantum well laser emitting at 1.5 μm
JPH0728080B2 (ja) * 1984-09-25 1995-03-29 日本電気株式会社 半導体超格子構造体

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US4835579A (en) 1989-05-30
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US4937204A (en) 1990-06-26
EP0201686B1 (de) 1991-02-20

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