DE3613215A1 - Verfahren zur herstellung eines halbleitersubstrats - Google Patents

Verfahren zur herstellung eines halbleitersubstrats

Info

Publication number
DE3613215A1
DE3613215A1 DE19863613215 DE3613215A DE3613215A1 DE 3613215 A1 DE3613215 A1 DE 3613215A1 DE 19863613215 DE19863613215 DE 19863613215 DE 3613215 A DE3613215 A DE 3613215A DE 3613215 A1 DE3613215 A1 DE 3613215A1
Authority
DE
Germany
Prior art keywords
substrate
semiconductor substrate
glass particles
silicon
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19863613215
Other languages
German (de)
English (en)
Other versions
DE3613215C2 (enExample
Inventor
Renshi Tokorozawa Saitama Sawada
Junji Kodaira Tokio/Tokyo Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of DE3613215A1 publication Critical patent/DE3613215A1/de
Application granted granted Critical
Publication of DE3613215C2 publication Critical patent/DE3613215C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Recrystallisation Techniques (AREA)
DE19863613215 1985-04-19 1986-04-18 Verfahren zur herstellung eines halbleitersubstrats Granted DE3613215A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60082609A JPH0618234B2 (ja) 1985-04-19 1985-04-19 半導体基板の接合方法

Publications (2)

Publication Number Publication Date
DE3613215A1 true DE3613215A1 (de) 1986-10-23
DE3613215C2 DE3613215C2 (enExample) 1989-07-20

Family

ID=13779215

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19863613215 Granted DE3613215A1 (de) 1985-04-19 1986-04-18 Verfahren zur herstellung eines halbleitersubstrats

Country Status (6)

Country Link
US (1) US4978379A (enExample)
JP (1) JPH0618234B2 (enExample)
KR (1) KR900005890B1 (enExample)
CA (1) CA1244968A (enExample)
DE (1) DE3613215A1 (enExample)
NL (1) NL189634C (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0335741A3 (en) * 1988-03-31 1991-01-30 Kabushiki Kaisha Toshiba Dielectrically isolated semiconductor substrate
WO2009015984A3 (de) * 2007-07-31 2009-05-22 Bosch Gmbh Robert Waferfügeverfahren mit senterschritt, waferverbund sowie chip

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07142571A (ja) * 1993-11-12 1995-06-02 Ube Ind Ltd 複合半導体基板及びその製造方法
US5639325A (en) * 1995-02-01 1997-06-17 The Whitaker Corporation Process for producing a glass-coated article
JPH08264636A (ja) * 1995-03-23 1996-10-11 Ube Ind Ltd 複合半導体基板
JPH08264637A (ja) * 1995-03-23 1996-10-11 Ube Ind Ltd 複合半導体基板
JPH08264643A (ja) * 1995-03-23 1996-10-11 Ube Ind Ltd 複合半導体基板
WO1997010184A1 (en) * 1995-09-12 1997-03-20 Corning Incorporated Boule oscillation patterns for producing fused silica glass
JP3979666B2 (ja) * 1995-09-12 2007-09-19 コーニング インコーポレイテッド 溶融シリカガラスの製造に於ける、炉、その使用方法及び炉によって製造された光学製品
EP0850201B1 (en) * 1995-09-12 2003-07-16 Corning Incorporated Containment vessel for producing fused silica glass
JPH10275752A (ja) 1997-03-28 1998-10-13 Ube Ind Ltd 張合わせウエハ−及びその製造方法、基板
RU2197768C2 (ru) * 1999-10-29 2003-01-27 Громов Владимир Иванович Способ изготовления полупроводниковой структуры
KR100499134B1 (ko) * 2002-10-28 2005-07-04 삼성전자주식회사 압축 접합 방법
JP6742593B2 (ja) * 2015-01-05 2020-08-19 日本電気硝子株式会社 支持ガラス基板の製造方法及び積層体の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3909332A (en) * 1973-06-04 1975-09-30 Gen Electric Bonding process for dielectric isolation of single crystal semiconductor structures
JPS5357978A (en) * 1976-11-05 1978-05-25 Hitachi Ltd Production of dielectric insulated and isolated substrate
US4393573A (en) * 1979-09-17 1983-07-19 Nippon Telegraph & Telephone Public Corporation Method of manufacturing semiconductor device provided with complementary semiconductor elements

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2272342A (en) * 1934-08-27 1942-02-10 Corning Glass Works Method of making a transparent article of silica
US2239551A (en) * 1939-04-22 1941-04-22 Corning Glass Works Method of making sealing glasses and seals for quartz lamps
US3768991A (en) * 1972-06-14 1973-10-30 Diacon Method for sealing an enclosure for an electronic component
DE2738614A1 (de) * 1976-09-01 1978-03-02 Hitachi Ltd Verfahren zum herstellen von halbleitersubstraten fuer integrierte halbleiterschaltkreise
JPS5330477A (en) * 1976-09-02 1978-03-22 Agency Of Ind Science & Technol Preparation of liquid drop
US4294602A (en) * 1979-08-09 1981-10-13 The Boeing Company Electro-optically assisted bonding
US4363647A (en) * 1981-05-14 1982-12-14 Corning Glass Works Method of making fused silica-containing material
JPS5844723A (ja) * 1981-09-11 1983-03-15 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
US4501060A (en) * 1983-01-24 1985-02-26 At&T Bell Laboratories Dielectrically isolated semiconductor devices
DD214836A1 (de) * 1983-04-26 1984-10-24 Werk Fernsehelektronik Veb Verfahren zum verbinden und hermetisieren von substraten mittels glaslot

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3909332A (en) * 1973-06-04 1975-09-30 Gen Electric Bonding process for dielectric isolation of single crystal semiconductor structures
JPS5357978A (en) * 1976-11-05 1978-05-25 Hitachi Ltd Production of dielectric insulated and isolated substrate
US4393573A (en) * 1979-09-17 1983-07-19 Nippon Telegraph & Telephone Public Corporation Method of manufacturing semiconductor device provided with complementary semiconductor elements

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
J. Appl. Phys. Lett. 43, 1 Aug. 1983, pp 263-265 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0335741A3 (en) * 1988-03-31 1991-01-30 Kabushiki Kaisha Toshiba Dielectrically isolated semiconductor substrate
WO2009015984A3 (de) * 2007-07-31 2009-05-22 Bosch Gmbh Robert Waferfügeverfahren mit senterschritt, waferverbund sowie chip

Also Published As

Publication number Publication date
NL189634B (nl) 1993-01-04
KR860008607A (ko) 1986-11-17
CA1244968A (en) 1988-11-15
NL8600983A (nl) 1986-11-17
US4978379A (en) 1990-12-18
JPH0618234B2 (ja) 1994-03-09
KR900005890B1 (ko) 1990-08-13
JPS61242033A (ja) 1986-10-28
DE3613215C2 (enExample) 1989-07-20
NL189634C (nl) 1993-06-01

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition