DE3587617D1 - Verfahren zur herstellung von bipolaren halbleiteranordnungen. - Google Patents

Verfahren zur herstellung von bipolaren halbleiteranordnungen.

Info

Publication number
DE3587617D1
DE3587617D1 DE85903877T DE3587617T DE3587617D1 DE 3587617 D1 DE3587617 D1 DE 3587617D1 DE 85903877 T DE85903877 T DE 85903877T DE 3587617 T DE3587617 T DE 3587617T DE 3587617 D1 DE3587617 D1 DE 3587617D1
Authority
DE
Germany
Prior art keywords
bipolar semiconductor
semiconductor arrangements
producing bipolar
producing
arrangements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE85903877T
Other languages
English (en)
Other versions
DE3587617T2 (de
Inventor
Yoichi Tamaki
Kazuhiko Sagara
Norio Hasegawa
Shinji Okazaki
Toshihiko Takakura
Hirotaka Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3587617D1 publication Critical patent/DE3587617D1/de
Publication of DE3587617T2 publication Critical patent/DE3587617T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/98—Utilizing process equivalents or options
DE85903877T 1984-08-10 1985-07-31 Verfahren zur herstellung von bipolaren halbleiteranordnungen. Expired - Fee Related DE3587617T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59166355A JPS6146063A (ja) 1984-08-10 1984-08-10 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3587617D1 true DE3587617D1 (de) 1993-11-11
DE3587617T2 DE3587617T2 (de) 1994-02-10

Family

ID=15829845

Family Applications (1)

Application Number Title Priority Date Filing Date
DE85903877T Expired - Fee Related DE3587617T2 (de) 1984-08-10 1985-07-31 Verfahren zur herstellung von bipolaren halbleiteranordnungen.

Country Status (6)

Country Link
US (1) US4729965A (de)
EP (1) EP0189486B1 (de)
JP (1) JPS6146063A (de)
KR (1) KR940001891B1 (de)
DE (1) DE3587617T2 (de)
WO (1) WO1986001338A1 (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0654795B2 (ja) * 1986-04-07 1994-07-20 三菱電機株式会社 半導体集積回路装置及びその製造方法
US4812417A (en) * 1986-07-30 1989-03-14 Mitsubishi Denki Kabushiki Kaisha Method of making self aligned external and active base regions in I.C. processing
JP2503460B2 (ja) * 1986-12-01 1996-06-05 三菱電機株式会社 バイポ−ラトランジスタおよびその製造方法
DE3683054D1 (de) * 1986-12-12 1992-01-30 Itt Ind Gmbh Deutsche Verfahren zum herstellen einer monolithisch integrierten schaltung mit mindestens einem bipolaren planartransistor.
DE3681291D1 (de) * 1986-12-18 1991-10-10 Itt Ind Gmbh Deutsche Kollektorkontakt eines integrierten bipolartransistors.
US4789885A (en) * 1987-02-10 1988-12-06 Texas Instruments Incorporated Self-aligned silicide in a polysilicon self-aligned bipolar transistor
JPS63253664A (ja) * 1987-04-10 1988-10-20 Sony Corp バイポ−ラトランジスタ
US5059546A (en) * 1987-05-01 1991-10-22 Texas Instruments Incorporated BICMOS process for forming shallow NPN emitters and mosfet source/drains
US4816423A (en) * 1987-05-01 1989-03-28 Texas Instruments Incorporated Bicmos process for forming shallow npn emitters and mosfet source/drains
US5214302A (en) * 1987-05-13 1993-05-25 Hitachi, Ltd. Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove
US4774204A (en) * 1987-06-02 1988-09-27 Texas Instruments Incorporated Method for forming self-aligned emitters and bases and source/drains in an integrated circuit
US4784966A (en) * 1987-06-02 1988-11-15 Texas Instruments Incorporated Self-aligned NPN bipolar transistor built in a double polysilicon CMOS technology
US4818713A (en) * 1987-10-20 1989-04-04 American Telephone And Telegraph Company, At&T Bell Laboratories Techniques useful in fabricating semiconductor devices having submicron features
JP2728671B2 (ja) * 1988-02-03 1998-03-18 株式会社東芝 バイポーラトランジスタの製造方法
KR900001034A (ko) * 1988-06-27 1990-01-31 야마무라 가쯔미 반도체장치
US5059544A (en) * 1988-07-14 1991-10-22 International Business Machines Corp. Method of forming bipolar transistor having self-aligned emitter-base using selective and non-selective epitaxy
EP0383610B1 (de) * 1989-02-17 1997-10-08 Matsushita Electronics Corporation Verfahren zum Herstellen einer Halbleitervorrichtung
US5227317A (en) * 1989-04-21 1993-07-13 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit bipolar transistor device
JPH02280340A (ja) * 1989-04-21 1990-11-16 Hitachi Ltd 半導体集積回路装置の製造方法
JPH07114210B2 (ja) * 1990-01-26 1995-12-06 株式会社東芝 半導体装置の製造方法
US4992848A (en) * 1990-02-20 1991-02-12 At&T Bell Laboratories Self-aligned contact technology
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法
US5138366A (en) * 1991-05-23 1992-08-11 Eastman Kodak Company Method of printing color borders with color prints and prints with integral borders
JP3132101B2 (ja) * 1991-11-20 2001-02-05 日本電気株式会社 半導体装置の製造方法
KR100242861B1 (ko) * 1992-04-27 2000-02-01 이데이 노부유끼 반도체장치의 제조방법
JPH07193075A (ja) * 1993-12-27 1995-07-28 Nec Corp 半導体装置およびその製造方法
US5846154A (en) 1996-10-15 1998-12-08 Handycare Single speed gear assembly for a wheelchair
US5786623A (en) * 1996-10-22 1998-07-28 Foveonics, Inc. Bipolar-based active pixel sensor cell with metal contact and increased capacitive coupling to the base region
US6043130A (en) * 1999-05-17 2000-03-28 National Semiconductor Corporation Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base
US6262472B1 (en) 1999-05-17 2001-07-17 National Semiconductor Corporation Bipolar transistor compatible with CMOS utilizing tilted ion implanted base
DE10134089A1 (de) * 2001-07-13 2003-01-30 Infineon Technologies Ag Verfahren zur Herstellung eines Bipolartransistors mit Polysiliziumemitter
US7880166B2 (en) * 2006-05-10 2011-02-01 Ho-Yuan Yu Fast recovery reduced p-n junction rectifier
US8669554B2 (en) 2006-05-10 2014-03-11 Ho-Yuan Yu Fast recovery reduced p-n junction rectifier
US7795103B2 (en) * 2006-05-19 2010-09-14 Ho-Yuan Yu Bipolar transistors with depleted emitter
US10553633B2 (en) * 2014-05-30 2020-02-04 Klaus Y.J. Hsu Phototransistor with body-strapped base

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS517398B1 (de) * 1970-11-13 1976-03-06
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors
JPS53132275A (en) * 1977-04-25 1978-11-17 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its production
US4160991A (en) * 1977-10-25 1979-07-10 International Business Machines Corporation High performance bipolar device and method for making same
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
US4236294A (en) * 1979-03-16 1980-12-02 International Business Machines Corporation High performance bipolar device and method for making same
US4392149A (en) * 1980-03-03 1983-07-05 International Business Machines Corporation Bipolar transistor
US4483726A (en) * 1981-06-30 1984-11-20 International Business Machines Corporation Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area
JPS5870570A (ja) * 1981-09-28 1983-04-27 Fujitsu Ltd 半導体装置の製造方法
JPS5866359A (ja) * 1981-09-28 1983-04-20 Fujitsu Ltd 半導体装置の製造方法
JPS5861668A (ja) * 1981-10-09 1983-04-12 Fujitsu Ltd 半導体装置の製造方法
JPS5946105B2 (ja) * 1981-10-27 1984-11-10 日本電信電話株式会社 バイポ−ラ型トランジスタ装置及びその製法
JPS58142573A (ja) * 1982-02-19 1983-08-24 Hitachi Ltd 半導体集積回路およびその製造方法
US4437897A (en) * 1982-05-18 1984-03-20 International Business Machines Corporation Fabrication process for a shallow emitter/base transistor using same polycrystalline layer
JPS5961179A (ja) * 1982-09-30 1984-04-07 Fujitsu Ltd バイポ−ラ半導体装置の製造方法
JPS59105363A (ja) * 1982-12-08 1984-06-18 Nec Corp 半導体装置の製造方法
DE3330895A1 (de) * 1983-08-26 1985-03-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von bipolartransistorstrukturen mit selbstjustierten emitter- und basisbereichen fuer hoechstfrequenzschaltungen
JPS6097626A (ja) * 1983-11-02 1985-05-31 Hitachi Ltd 半導体装置における微細孔の形成方法および半導体装置の製造方法

Also Published As

Publication number Publication date
DE3587617T2 (de) 1994-02-10
KR940001891B1 (ko) 1994-03-10
WO1986001338A1 (en) 1986-02-27
EP0189486A1 (de) 1986-08-06
US4729965A (en) 1988-03-08
EP0189486A4 (de) 1987-01-20
JPS6146063A (ja) 1986-03-06
KR860700315A (ko) 1986-08-01
EP0189486B1 (de) 1993-10-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee