DE3424085C2 - - Google Patents

Info

Publication number
DE3424085C2
DE3424085C2 DE3424085A DE3424085A DE3424085C2 DE 3424085 C2 DE3424085 C2 DE 3424085C2 DE 3424085 A DE3424085 A DE 3424085A DE 3424085 A DE3424085 A DE 3424085A DE 3424085 C2 DE3424085 C2 DE 3424085C2
Authority
DE
Germany
Prior art keywords
layer
semiconductor layer
insulating layer
strip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3424085A
Other languages
German (de)
English (en)
Other versions
DE3424085A1 (de
Inventor
Kazuaki Sorimachi
Etsuo Yamamoto
Hiroshi Tanabe
Katsumi Aota
Kanetaka Sekiguchi
Seigo Tokorozawa Saitama Jp Togashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP58117488A external-priority patent/JPH0652794B2/ja
Priority claimed from JP58122205A external-priority patent/JPS6014468A/ja
Priority claimed from JP58136162A external-priority patent/JPS6028276A/ja
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Publication of DE3424085A1 publication Critical patent/DE3424085A1/de
Application granted granted Critical
Publication of DE3424085C2 publication Critical patent/DE3424085C2/de
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/868PIN diodes
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1365Active matrix addressed cells in which the switching element is a two-electrode device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Liquid Crystal (AREA)
DE19843424085 1983-06-29 1984-06-29 Verfahren zur herstellung von hoechstminiaturisierten duennschichtdioden Granted DE3424085A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP58117488A JPH0652794B2 (ja) 1983-06-29 1983-06-29 薄膜ダイオードの製造方法
JP58122205A JPS6014468A (ja) 1983-07-05 1983-07-05 薄膜ダイオ−ド
JP58136162A JPS6028276A (ja) 1983-07-26 1983-07-26 薄膜ダイオ−ドの製造方法

Publications (2)

Publication Number Publication Date
DE3424085A1 DE3424085A1 (de) 1985-01-17
DE3424085C2 true DE3424085C2 (US20100056889A1-20100304-C00004.png) 1989-05-03

Family

ID=27313386

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19843424085 Granted DE3424085A1 (de) 1983-06-29 1984-06-29 Verfahren zur herstellung von hoechstminiaturisierten duennschichtdioden

Country Status (3)

Country Link
DE (1) DE3424085A1 (US20100056889A1-20100304-C00004.png)
FR (1) FR2548450B1 (US20100056889A1-20100304-C00004.png)
GB (1) GB2144266B (US20100056889A1-20100304-C00004.png)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2579775B1 (fr) * 1985-04-02 1987-05-15 Thomson Csf Procede de realisation d'elements de commande non lineaire pour ecran plat de visualisation electro-optique et ecran plat realise selon ce procede
FR2579809B1 (fr) * 1985-04-02 1987-05-15 Thomson Csf Procede de realisation de matrices decommande a diodes pour ecran plat de visualisation electro-optique et ecran plat realise par ce procede
FR2581781B1 (fr) * 1985-05-07 1987-06-12 Thomson Csf Elements de commande non lineaire pour ecran plat de visualisation electrooptique et son procede de fabrication
NL8702490A (nl) * 1987-10-19 1989-05-16 Philips Nv Weergeefinrichting met laterale schottky-dioden.
NL8802409A (nl) * 1988-09-30 1990-04-17 Philips Nv Weergeefinrichting, steunplaat voorzien van diode en geschikt voor de weergeefinrichting en werkwijze ter vervaardiging van de steunplaat.
FR2714765B1 (fr) * 1993-12-30 1996-02-02 France Telecom Procédé de réalisation d'une connexion électrique entre deux couches conductrices.
DE4410799C2 (de) * 1994-03-29 1996-02-08 Forschungszentrum Juelich Gmbh Diode
GB2304993B (en) * 1995-08-23 1997-08-06 Toshiba Cambridge Res Center Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4174217A (en) * 1974-08-02 1979-11-13 Rca Corporation Method for making semiconductor structure
US4425379A (en) * 1981-02-11 1984-01-10 Fairchild Camera & Instrument Corporation Polycrystalline silicon Schottky diode array
EP0071244B1 (en) * 1981-07-27 1988-11-23 Kabushiki Kaisha Toshiba Thin-film transistor and method of manufacture therefor
US4642620A (en) * 1982-09-27 1987-02-10 Citizen Watch Company Limited Matrix display device

Also Published As

Publication number Publication date
GB2144266B (en) 1987-03-18
DE3424085A1 (de) 1985-01-17
FR2548450A1 (fr) 1985-01-04
GB2144266A (en) 1985-02-27
FR2548450B1 (fr) 1987-04-30
GB8416632D0 (en) 1984-08-01

Similar Documents

Publication Publication Date Title
DE3587485T2 (de) Flüssigkristall-anzeige-element und dessen herstellung.
DE3587536T2 (de) Flüssigkristall-anzeigeelement und verfahren zu dessen herstellung.
EP0239652B1 (de) Verfahren zum Herstellen einer monolithisch integrierten Schaltung mit mindestens einem bipolaren Planartransistor
DE68917654T2 (de) Anzeigevorrichtung.
DE69017262T2 (de) Aktiv-Matrix-Anzeigevorrichtung und Verfahren zu ihrer Herstellung.
DE2312413B2 (de) Verfahren zur herstellung eines matrixschaltkreises
DE3117950A1 (de) Planare duennfilmtransistoren, transistoranordnungen und verfahren zu ihrer herstellung
DE2732184A1 (de) Halbleitervorrichtung und verfahren zu ihrer herstellung
DE4344897A1 (de) Verfahren zur Herstellung von Dünnfilmtransistoren
DE2911132A1 (de) Verfahren zur bildung einer kontaktzone zwischen schichten aus polysilizium
DE3788470T2 (de) Verfahren zur Herstellung eines Feldeffekttransistors mit isoliertem Gate.
DE102004048723A1 (de) Herstellverfahren für ein Dünnschichttransistorarray-Substrat
DE3043289A1 (de) Herstellungverfahren fuer eine halbleitereinrichtung
DE4426311B4 (de) Leiterbahnstruktur eines Halbleiterbauelementes und Verfahren zu ihrer Herstellung
DE2315761B2 (de) Verfahren zur Herstellung einer integrierten Schaltung aus Oberflächen-Feldeffekttransistoren
DE3424085C2 (US20100056889A1-20100304-C00004.png)
DE19724245A1 (de) Flüssigkristallanzeige und Herstellungsverfahren dafür
DE2746335C2 (US20100056889A1-20100304-C00004.png)
DE2645014C3 (de) Verfahren zur Herstellung einer integrierten MOS-Schaltungsstrukrur mit doppelten Schichten aus polykristallinem Silizium auf einem Silizium-Substrat
DE2854994C2 (de) Halbleiteranordnung mit einem Transistor und einem mit dem Basisgebiet des Transistors verbundenen Widerstand
DE3226097C2 (US20100056889A1-20100304-C00004.png)
DE69629974T2 (de) Verfahren zur Herstellung einer integrierten Schaltung mit komplementären Bipolartransistoren
DE69012078T2 (de) Methode zur Herstellung eines Schottkydioden-Bauelements.
DE102017101511B4 (de) Verfahren zur Herstellung eines Matrixsubstrats, Matrixsubstrat, Anzeigefeld und Anzeigevorrichtung
DE3730953C2 (US20100056889A1-20100304-C00004.png)

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee