GB2144266A - Method of manufacture for ultra-miniature thin-film diodes - Google Patents
Method of manufacture for ultra-miniature thin-film diodes Download PDFInfo
- Publication number
- GB2144266A GB2144266A GB08416632A GB8416632A GB2144266A GB 2144266 A GB2144266 A GB 2144266A GB 08416632 A GB08416632 A GB 08416632A GB 8416632 A GB8416632 A GB 8416632A GB 2144266 A GB2144266 A GB 2144266A
- Authority
- GB
- United Kingdom
- Prior art keywords
- semiconductor layer
- layer
- lower electrode
- elongated
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 51
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 130
- 239000010408 film Substances 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000000059 patterning Methods 0.000 claims abstract description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 5
- 238000010276 construction Methods 0.000 claims description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
- 229910052905 tridymite Inorganic materials 0.000 claims description 5
- 238000005286 illumination Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 238000010884 ion-beam technique Methods 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 239000012780 transparent material Substances 0.000 claims 1
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 10
- 238000000151 deposition Methods 0.000 abstract 1
- 239000012212 insulator Substances 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 101100179596 Caenorhabditis elegans ins-3 gene Proteins 0.000 description 1
- 238000000149 argon plasma sintering Methods 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1365—Active matrix addressed cells in which the switching element is a two-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Nonlinear Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Mathematical Physics (AREA)
- Liquid Crystal (AREA)
Abstract
A thin-film diode is formed by a semiconductor layer (14) sandwiched between the intersections of and upper (18) and lower (12) electrodes, each of narrow elongated form, portions of an insulating film (19) being disposed between the upper electrode (18) and the edges of the semiconductor layer (14) and the lower electrode (12). The diode is produced by depositing a PIN a-Si layer structure on a conductive layer and patterning to form an elongate strip. An insulating layer is deposited and processed to expose the upper face of the semiconductor strip. A second conductive layer is deposited and patterned to form the upper electrode extending transversely to the strip. The excess semiconductor and insulator is then etched away using the upper electrode as a mask. Variations of the process are described. A pair of diodes connected in inverse parallel may be used as a switching element for a liquid crystal display and occupy a small substrate area due to the self aligned contact. <IMAGE>
Description
SPECIFICATION
Method of manufacture for ultra~miniature. thin-film diodes
In recent years, liquid crystal matrix display panels have come into widespread use in a. variety of applications. In certain recent applications of such panels, e.g. miniature television displays, it.is necessary to produce a very high density of display elements within arelatively small display area, so that.eaqh.display element must be of minute size.
Although the passive type of liquid crystal matrix display.. panel has been extensively used in the past, i.e. a display panel in which no drive.control-element is associated with each display element, these do not provide the capability for high display element density which is necessary for applications such as
TV displays. -Hence ithas been found necessary to utilize "active matrix" liquid crystal display panels for-such displays. With an "active matrix" display panel,.each display element is coupled to an-indi vidual drive control element, which controls the potential applied to the display elem#nt from#the drive electrodes of the matrix.In the past,thin-film transistors have generally been used as the active elements in such display panels. However the forme tion otvery large numbers of thin-film transistors presents various manufacturing problems, such as the difficulty of attaini.ng asatisfactory manufacturing yield, and in addition the. manufacturing process is relatively complex, so that the cost of.producing sudh. display panels is high.In addition, the panel area occupied by the active elements of such a display panel is an important factor., when the display size is small and the display element density is high, i.e. if the area occupied by each active element is not sufficiently small-by comparison with the display element size, the aperture ratio of the display will be lowered, resulting in reduced display brightness and contrast. Thus it is desirable to utilize active elements-which can be manufactured more inexpensively than thin-film transistors and which can also be made to occupy a minimum of display area.
It has recently been found (as disclosed in
Japanese patent No. 57-167945) that it is possible to use .non-linear resistance element formed-of~diode rings as satisfactory active elements in such display panels. A diode ring is a 2-terminal element, general lycomprising#a. pair of diodes which are connected in parallel with one another, with opposed polarities, i.e. connected in.a ring configuration. When used as active elements of a. liquid crystal display panel, thin-film- diodes are utilized, with the semiconductor material generally being amorphous silicon. Such diode rings offer certain important advantages, one of which is that drive control of the display elements is achieved by utilizing the forward conduction characteristic of the diodes.This characteristic is extremely stable and can readily be controlled at the stage of manufacture. However with prior art methods offorming an array of such thin-film diodes on a substrate, it is not possible to reduce the area occupied.by each diode below a certain value, which is greater than that which is possible on the basis of etching dimensional limitations alone.This problem results from the structure of such a prior art thin-film diode, which basically comprises a lower electrode, i.e. a narrow metallic strip formed on the substrate, an,approximately square-shaped layer of semiconductor material formed on the lower electrode, a film of insulating material formed over the semiconductor layer and-surrounding areas of the lower electrode, with a contact hole being formed through the portion of the insulating film which covers the upper face of the semiconductor layer, and an upper electrode which is-formed over the insulating film such as to- contact the semiconductor layer upper face through the contact hole and is insulated from the lower electrode by the insulating film.
-~These contact holes are formed by a patterning process, em ploying a mask and etching of the insulating film to form the holes. Since the mask can only be aligned to a certain degree of accuracy, some-tolerance must be allowed for positioning the contact holes with respectto the semiconductor layer, and as a result, the area occupied by the diode cannot be made smallerthan the determined by this contact hole alignment tolerance.
It is an objective of the present invention to overcome the disadvantage of prior art methods of manufacturing thin-film diodes, by providing a diode structure and- a -method of manufacturing whereby the substrate area occupied by each diode can be reduce to the absolute minimum, with no necessity to increase the diode area above that minimum due to alignment tolerance requirements. As- a result, the area occupied by a thinwfilm diode manufactured according to the present invention can be made equal to the area of intersection between two narrow metallic strips which- serve as connecting leads and diode electrodes, and hence can be made as small as 4 micronmeters square.The method of manufacturing according to the present invention basically comprises the steps of forming a two-layer elongated strip upon-an electrically insulating substrate, this two-layer strip comprising-a lower electrode formed of a metallic material.with layer of suitably doped semiconductor material (e.g. a PIN layer of amorphous silicon) formed over the lower electrode, forming a film of insulating material (e.g.SiO2) over this two-layer strip, removing the portion of the insulating film which covers the upper face of the semiconductor layer while leaving the sde faces of the semiconductor layer while leaving the side faces of the semiconductor layer and the lower electrode covered by the insulating film, then forming an elongated metallic strip as an upper electrode over the two-layer strip to thereby contact the upper face of the semiconductor layer while being insulated from the side faces of the semiconductor layer and the lower electrode. This upper electrode thereby forms a diode electrode and a connecting lead, i.e. a diode structure is formed at the intersection between the lowerelectrode and the upper electrode. Unnecessary portions of the semiconductor layer (its.
portions ofthe semiconductor layer other than that sandwiched between the intersection of the upper and lower electrodes) are removed, partially or entirely, either before or after the upper electrode is formed.
If the unnecessary semiconductor layer portions are to be removed after the upper electrode has been formed, then the upper electrode itself can conveniently be used as a mask for etching removal of these semiconductor layer portions. Alternatively, if the unnecessary semiconductor layer portions are removed prior to formation of the upper electrode, then the upper electrodes of two adjacent diodes can be arranged to serve also as interconnecting leads to form a diode ring, without the need for an additional manufacturing step being required to form these interconnecting leads.
Since the exposure of the upper face of the semiconductor layer, to enable contact with the upper electrode, is performed by substantially entire removal of the insulating film portion covering the upper face of the semiconductor layer, rather than one specific portion of that insulating film, there is no possibility of misalignment occurring such as may occur with the use of contact holes.
Figure 1(aj and 1(b) are plan and cross-sectional views to illustrate a prior art construction and method of manufacture of a thin-film diode;
Figure 2(a) and 2(b) are diagrams for illustrating the effects of connection hole alignment tolerance upon the minimum size of such a prior art thin-film diode;
Figure 3 is an oblique view to illustrate an embodimenet of a thin-film diode manufactured by a first method according to the present invention, and
Figures 4(a) to 4(e) are oblique view to illustrate stages in the latter method of manufacture;
Figure 5 is a graph showing the forward and reverse conduction characteristics of a thin-film diode manufactured according to the present invention;;
Figure 6 is a cross-sectional diagram to illustrate the relationship between the lower electrode and semiconductor layer side of faces of a thin-film diode manufactured by the method of the present invention, and portions of an insulating film which cover these side faces;
Figure 7(a) to 7(f) are oblique views to illustrate stages in a second method ofthin-film diode manufacture according to the present invention;
Figure 8 is a circuit diagram of a diode ring formed of two diodes;
Figure 9(a) and 9(b) are a plan view and a cross-sectional view respectively to illustrate a prior art method of manufacturing a diode ring formed of thin-film diodes;;
Figure 10 is a diagram to illustrate patterning steps in a method of manufacturing a diode ring formed of thin-film diodes according to the present invention;
Figure 11(a) to 11(e) are cross-sectional views to illustrate stages in the latter method of manufacturing a diode ring;
Figure 12/at to 12(d) are plan views to illustrate stages in the latter method of manufacturing a diode ring; and
Figure 13 is a cross-sectional view to illustrate a modification of the structure of a thin-film diode manufactured according to the present invention.
Before describing the configuration and the method of manufacture of a thin-film diode according to the present invention, a typical prior art configuration and manufacturing method will be utlined. Figure 1 (a) and 1 (b) are a plan view and a cross-sectional view (taken through lines A-A') respectively of a prior art type of thin-film diode, which is formed as part of an array of thin-film diodes on a substrate 10, with a lower electrode 2 and a semiconductor layer 3 being firstformed successively on the substrate, then an insulating film 4 being formed over these.A contact hole 16 is then formed in the portion of the insulating film which covers the upper face of the semiconductor layer, to expose a portion of that upper face, and an upper electrode 5 is formed over the other layers to complete the diode structure. As shown, the upper electrode is positioned over the contact hole 16, to thereby contact the upper face of the semiconductor layer 3, and is insulated from the side faces of the semiconductor layer and from the lower electrode by the insulating film 4. A photo-lithographytechni- que is used to form the contact hole 16, so that there will be some degree of error in positioning these holes with respect to the position of the semiconductor layer.This is illustrated in the plan and crosssectional view of Figures 2(a) and 2(b) respectively, which show the relationship between the size of the diode structure and the contact hole alignment tolerance which must be provided to allow for the latter positioning error. The necessary contact hole alignment tolerance is indicated by numerals 8. It will be apparent that if insufficient contact hole alignment tolerance is allowed, i.e. the size of the diode structure is not sufficiently large (i.e. with respect to substrate area covered), then misalignment of the contact hole may result in a portion of the side face of the semiconductor layer 3 becoming exposed at the time of forming the contact hole.
Thus, when the upper electrode is subsequently formed, this may effectively short-circuit the internal structure of the diode, i.e. if the semiconductor layer 3 comprises a successive PIN layered construction, then the PIN layers may be short-circuited by the upper electrode, thereby rendering the diode operation ineffective or causing some deterioration of the diode operating characteristics.
As a result, it is necessary to allow a contact hole alignment tolerance which is approximately equal to the length of each side of the contact hole (assuming the latter to be square-shaped as seen in plan). The minimum practicable size for such a contact hole at present is typically about 6 micronmeters, so that this necessary tolerance factor will increase the minimum practicable size of the diode structure to approximately 20 micronmeters square.
Thus, if such thin-film diodes are used to form non-linear resistance element of a liquid crystal matrix display panel in which the display elements are of very small size, the aperture ratio of the display will be reduced due to the relatively large display area occupied by the diodes.
With the configuration and method of manufacturing of a thin-film diode according to the present invention, however, it is unnecessary to allow such a contact hole alignment tolerance, as will be made apparent from the following embodiments. Figure 3 is an oblique view of an example of a thin-film diode manufactured according to the present invention.
This comprises a substrate 10, on which is formed a lower electrode 12, with a semiconductor layer 14 formed over the lower electrode 12. The semiconductor layer 14 is formed of amorphous silicon, and has a successive PIN layered internal configuration.
An insulating film 19 is disposed as shown, such as to insulate the side faces of lower electrode 12 and semiconductor layer 14 (extending along the direction of elongation of lower electrode 12) from an
upper electrode 18 formed thereon, and to insulate lower electrode 12 from upper electrode 18, while the upper face of semiconductor layer 14 is substantially entirely exposed to contact with upper electrode 18.
The process of manufacturing a diode having such a a structure will now be described, referring to
Figures 4(a) to 4(e). First, a layer of metallic material is formed on an optically transparent electrically non-conductive substrate 10, then a layer of semiconductor material, e.g. amorphous silicon having a
PIN internal layered structure, is formed over the metallic layer. These two layers are patterned simultaneously, to form a elongated two-layer strip comprising an elongated metal strip which will be referred to as the lower electrode 12, with a precisely corresponding strip of semiconductor layer 14 being thereby formed over lower electrode 12 as illustrated in Figure 1(a).
As shown, the external faces of this two-layer strip comprise side faces 1 2a, 1 4a of lower electrode 12 and semiconductor layer 14 respectively, and the upper face 14b of semiconductor layer 14. A thin film 19 of an insulating material, e.g. SiO2 is then formed over this two-layer strip and the surrounding area of substrate 10, and a layer of photo-sensitive etching resist material is formed over insulating film 19.
Light rays 28 are then directed onto the rear face of substrate 10, as shown in Figure 4)b). The resist layer 26 is then developed, and the portions of the resist which has not been subjected to illumination in the preceding step (i.e. the portion covering the upper face 14b of semiconductor layer 14., shielded from light 12 by semiconductor layer 14 and lower electrode 12) are removed. Etching is now carried out to remove all portions of the insulating film which are not covered by resist, this etching being performed to a depth at least equal to that of the thickness of the insulating film 19. In this way, the portion of insulating film 19 covering the upper face 14b of semiconductor layer 14 is substantially entirely removed. The resultant structure is as illustrated in Figure 4(c), after the remaining portions of resist have been removed.
It will be apparent that such a procedure will result in the side faces 12a, 14a of the lower electrode 12 and semiconductor layer 14 being left covered with portions 20 of the insulating film 19, while the upper face 14b of semiconductor layer 14 is now free of a covering of insulating film. The positions and areas of those portions of insulating film 19 which are respectively removed from two-layer strip 15 and left
to insulate the side faces thereof are thereby self
defined, by the shape of two-layer strip 15, and are
not determined by an etching mask pattern. Thus,
the width of the portion of semiconductor layer 14
that is uncovered from the insulating film 19 is made
almose precisely equal to the width of two-layer strip
15, i.e. the width of lower electrode 12.
Next, a second metallic layer is formed over the
previously formed layers, and is patterned to form
an upper electrode 18, having the form of an
elongated strip which intersects the direction of
elongation of lower electrode 12 at an oblique angle,
i.e. perpendicular to that direction, as illustrated in
Figure 4(d). Patterning of semiconductor layer 14
and insulating film 19 is then performed, using
upper electrode 18 as a mask, to thereby remove all
portions of semiconductor layer 14 other than that
lying directly between the areas of overlap of lower
electrode 12 and upper electrode 18, i.e. by performing etching to a depth at least equal to that of semiconductor layer 14. The resultant structure of the completed thin-film diode is as shown in Figure 4(e), the diode being formed at the intersection between upper electrode 18 and lower electrode 12.
Such a diode occupies the minimum possible amount of substrate area.
It will be seen from the above that deviations in the etching pattern whereby upper electrode 18 is formed will have absolutely no effect upon the final diode structure, which will invariably be formed directly between the areas of intersection of upper electrode 18 and lower electrode 12, with the side faces of the semiconductor layer and lower electrode 12 adjacent to upper electrode 18 being completely insulated therefrom by portions of the insulating film. Thus, pattern alignment tolerance factors have no effect upon the possible diode size, which is determined solely by the widths of upper electrode 18 and lower electrode 12. With present-day technology, these widths can be as small as 6 micronmeters, so that a diode covering a substrate area approximately 6 micronmeters square can be realized.
Suitable material for substrate 10 is Corning 7059 borosilicate glass, while upper electrode 12 can be formed of successively deposited layers of Ins3: Sn (ITO) and Cr. The semiconductor layer 14 comprises a layer of amorphous silicon having a PIN layered structure. Insulating film 6 is SiO2, formed by plasma
CVD. Upper electrode 18 is formed of successively deposited layers of Cr and Al. Removal of the insulating film portion from the upper face of semiconductor layer 14 (from step 4(b) to 4(c) described above) is performed using an oxidizing buffer film etching solution. Patterning of the semiconductor layer and insulating film to attain the condition shown in step 4(e) is preferably carried out by reactive ion etching (RIE).
Figure 5 is a graph showing the forward and reverse conduction characteristics, designated by numerals 30 and 31 respectively, of a thin-film diode manufactured by the method of the present invention described above. Diodes having such characteristics are satisfactory for use in forming non-linear resistance element for drive control of display elements on a liquid crystal matrix display panel, i.e.
provide non-linear resistance element having suitable threshold characteristics.
As stated above, a thin-film diode manufactured by the method of the present invention can be made as small as 6 micronmeters square. In the prior art, the minimum size which has been practicable for such diodes is approximately 20 micronmeters square. Thus, use of the diode structure and manufacturing method of the present invention enable the substrate area occupied by each diode to be substantially reduced, and in addition provide a substantial reduction in the internal capacitance of the diode.
In the method of manufacture described above, rear illumination of the substrate is employed, in conjunction with a photo-sensitive etching resist, to define the area of insulating film which is to be removed from the upper face of the semiconductor layer. If a suitably high lever of illumination is applied at this stage, then some scattering of the light will occur, which will have a beneficial effect as will now be described. Referring to Figure 6, such light scattering will result in exposure to light, and subsequent development, of a small portion of resist which slightly overlaps the boundary of the upper face of the semiconductor layer 14. When the non-exposed portions of resist are then removed, and etching of the uncovered area of the insulating film 19 performed, the final result will be as shown in
Figure 6.Portions 34 of insulating film side portions 20 will overlap the border of the upper face 14b of semiconductor layer 14, thereby reliably ensuring that the side faces of semiconductor layer 14 and lower electrode 12 will be reliably covered by insulating film and hence completely insulated from upper electrode 18, in spite of deviations in the depth to which etching of the insulating film is performed, deviations in the thickness of insulating film 19 when first deposited, variations in the quality of insulating film 19 (e.g. resulting from low-temperature growth of the SiO2film), etc. This covering of the extreme border portions of upper face 14b of semiconductor layer 14 will have no perceptible effect upon the minimum size of diode which can be attained, and will ensure that the diode characteristics will be
perfectly uniform.
A second example of the manufacturing method
of the present invention will now be described,
referring to Figures 7(a) to 7(f). The firsttwo stages in this process, whereby an elongated two-layer strip
15 is formed, comprising a lower electrode 12 with a semiconductor layer 14 formed thereon, and where
by an insulating film of SiO2 is formed over these
layers, with the resultant structures being as shown
in Figure 7(a) and 7(b), are identical to those of the
example of Figure 4(a) to 4(e) described hereina
bove. However a different method is employed to
remove the portion of insulating film 19 which
covers the upper face 14b of semiconductor layer 14.
As shown in Figure 7(c), reactive ion etching (RIE) as
indicated by numeral 36 is utilized. This is applied to
insulating film 19 in an anisotropic manner, as it has
been found that this provides more rapid and
uniform etching than is possible with reactive ion etching performed in a single direction, e.g. perpendicularto the substrate plane.
This etching is continued to a sufficient depth to remove the portion of insulating film 19 covering upper face 14b of semiconductor layer 14 of the two-layer strip 15, with the final result being as indicated in Figure 7(d). As shown, side faces 14a, 12a of semiconductor layer 14 and lower electrode 14 respectively are left completely covered by insulating film portions 20, with the upper face 14b of semiconductor layer 14 being left exposed. It will be apparent that the position and extent of this exposed upper face 14b and of the insulating film portions which cover sides 14a, 12a of semiconductor layer 14 and lower electrode 12 are determined in a self-defined manner, i.e. by the shape of the original two-layer strip 15 and the duration of the latter etching process, and are not determined by an etching mask pattern.
Thereafter, as in the example of Figure 4(a) to (e), a second metallic layer 40 is formed over the previously formed layers, and is etched to form an upper electrode 18 which is a narrow elongated metal strip disposed to intersect lower electrode 12 substantially perpendicularly. Etching of the unnecessary portions of semiconductor layer 14 extending on either side of upper electrode 18 is then performed, to remove these portions, using upper electrode 18 as a mask. Thus, as in the previous example, the final diode structure basically comprises the portion of semiconductor layer 14 which is left sandwiched between the areas of intersection of lower electrode 12 and upper electrode 18.
With this example of the method of the present invention, as with the previous example, any alignment errors in the processes whereby two-layer strip 15 and upper electrode 18 are formed by patterning will have no effect whatsoever upon the structure or operating characteristics of the completed diode, since the diode is formed at the intersection between the upper and lower electrodes.
Figure 8 is a circuit diagram of a diode ring, which can be used as a non-linear resistance element to control driving of a display element of a liquid crystal matrix display panel. This simply consists of two diodes, 44 and 46, connected in parallel with opposing polarities to form a 2-terminal element.
Figures 9a and 9b are a plan view and a crosssectional view (taken through line A-A" in Figure 9a) of an example of a prior art method of forming such a diode ring, using thin-film diodes. Each thin-film diode is formed as described hereinabove with reference to Figures 1 (a) and 1(b), with corresponding reference numerals being employed. In this example, the lower electrode 2 of each diode serves as one of the terminals of the diode ring, i.e. as one of terminals 48, 50 shown in Figure 8, while each of the upper electrodes 5 of the diodes serves to connect to the lower electrode of the opposite diode.
Such a structure has the disadvantages described hereinabove with reference to Figures 1(a), 1(b), i.e.
due to the need to allow for contact hole alignment tolerance, it is necessary to increase the amount of substrate area occupied by each diode such as to be substantially greater than that actually required for diode operation. That is to say, a portion of the insulating film 4 is left sandwiched between the upperface of semiconductor layer3 and upper electrode 5, around contact hole 16, and the portion of semiconductor layer 3 lying below the latter insulating film portion is in fact ineffective with regard to diode operation, i.e. only the portion of semiconductor layer 3 lying between the contact hole 16 and lower electrode 2 is effective. This ineffective semiconductor layer portion acts to reduce the display aperture ratio, when such diode rings are formed on a liquid crystal matrix display panel.However, with a diode manufactured according to the present invention, as described above, it is possible to completely eliminate all unnecessary portions of the semiconductor layer, to ensure that the minimum possible amount of substrate area is occupied by each diode.
It will be apparent that the thin-film diode structures formed by the methods described above with reference to Figures 4(a) to (e) and 7(a) to (f) can be readily used to form diode rings. That is to say, a closely adjacent pair of two-layer strips 15 can be formed, and the patterning arranged such that, after to the stage of formation of the upper electrodes, a further patterning step is performed to interconnect the upper and lower electrodes of the adjacent diodes, to form a diode ring. There would be no need to form contact holes for this purpose, such as are required with the prior art structure of Figures 9(a), 9(b). However it is also possible to modify the method of the present invention to enable even simplerformation of diode rings, as will be de scribedwith reference to Figures 10,11 and 12.
Figure 10 is a plan view showing the etching mask patterns which are successively used with this method, while Figures 11 (a) to 11 (f) show crosssectional views taken along lines A-A' -A" in Figure 10 to illustrate successive steps in the manufacturing process, and Figures 12(a) to 12(d) are plan views to illustrate these successive steps. in a first patterning step, pattern 70 shown in Figure 10 is used to etch an adjacent pair of two-layer strips, each comprising a lower electrode and a semiconductor layer which are designated as 12a, 14a and 12b, 14b for the left and right side strips shown in the diagrams respectively.
A layer of etch resist, 76a, 76b, is left as the uppermost layer of each strip, and this resist layer is left in place when the next step of applying a film of insulating material is performed, as shown in Figure 11 b, in order to simplify the manufacturing process.
Next, the resist layers and the portions of the insulating film layer covering the upper faces of the semiconductor layer portions 14a, 14b are removed, to produce the structure shown in Figures 11 (c) and 12(b), with the side faces of the insulating film layers and lower electrodes being covered by insulating film portions 20 as in the previous embodiments.
Patterning is now performed, using etching patterns as denoted by numeral 72 in Figure 10, whereby all of the semiconductor layer layer other a pair of slightly elongated rectangular portions 14a', 14b' are removed, as illustrated in Figures 11 (d) and 12(c), with the side faces of these portions 14a', 14b' along the direction of elongation of the lower electrodes being covered by corresponding insulating film portions 20.
A second metallic layer is then formed over the previously formed layers, and upper electrodes 18a, 18b are formed by patterning of this second metallic layer, using etching pattern 74 in Figure 10. As shown in Figure 12)d), each of upper electrodes 18a, 18b comprises an elongated strip. Electrode 18a is disposed to lie over semiconductor layer portion 14a' and lower electrode 12b, while upper electrode 18b is disposed to lie over semiconductor layer portion 14b' and lower electrode 12a. In this way, a first thin-film diode is formed at the intersection between lower electrode 12a and upper electrode 18a, while a second thin-film diode is formed at the intersection between lower electrode 12b and upper electrode 8bj, with these diodes being connected as a diode ring.Upper electrode 18a and lower electrode 12a can be extended, as shown in Figure 12(d), to be used as connecting leads to this diode ring.
This construction and method of manufacture for the diodes differs from the previous examples in that, since the semiconductor layer portions 14a', 14b' which are to be used to form the diodes are each formed prior to the formation of the upper electrodes 18a, 18b, it will necessary to make each of these semiconductor layer portions 14a', 14b' slightly longer than the width of the upper electrodes. This is in order to allow a certain amount of pattern alignment tolerance (only along the direction of elongation of the lower electrodes) in the patterning of upper electrodes 18a, 18b. However it should be noted that the resultant small portions of unnecessary semiconductor layer which are left on either side of upper electrodes 18a, 18b in this case, i.e.
extending along the direction of elongation of the lower electrodes 12a, 12b, will result in no increase in the substrate area occupied by each diode, by comparison with the diode embodiments of the present invention described hereinabove. Thus, this method of forming thin-film diodes and at the same time interconnecting the diode electrodes to form a diode ring, provides the same advantages of small diode size, with low internal capacitance, which have been described hereinabove for the previous embodiments of the invention If desired, it would of course be possible to perform a further step of etching, using upper electrodes 18a, 18b as masks to remove the small excess portions of semiconductor layer described above.
In the descriptions of the embodiments given above, it has been assume that the upper and lower electrodes of the diodes respectively contact the upper and lower faces of the semiconductor layer directly, e.g. with the lower electrode contacting the
N-doped layer and the upper electrode contacting the P-doped layer of a PIN semiconductor layer.
However it is possible to provide intermediate layers between the upper electrode and lower electrode and the semiconductor layer, as illustrated in the cross-sectional view of Figure 13. Here, intermediate layers 96 and 98 are formed respectively between a upper electrode 18 and a P-doped region of the semiconductor layer 19, and between lower electrode 12 and an N-doped region. Such intermediate layers can be of various types and have various function, such as providing improved contact between the upper and lower electrodes and the semiconductor layer, shielding the semiconductor layer against incident light, etc. Such intermediate layers can be formed between the semiconductor layer and both the upper and the lower electrodes, or only one of the electrodes. Suitable materials for such intermediate layers include metals such as Cr,
Al, Mo, etc.
From the above, twill be apparentthatthe configuration and method of manufacture of thin- film diodes according to the present invention enables such diodes to be made substantially smaller in size than has been possible with prior art techniques, thereby greatly facilitating the use of such diodes (in the form of diode rings) as non-linear resistance elements formed on a high display density liquid crystal matrix display panel to control driving of the display elements.
In the above, the method of the present invention has been described as for the manufacture of single diodes and single diode ring elements. However it will be appreciated that in practice the method would be applied to the simultaneous manufacture of a large number of elements arrayed upon a substrate, and that the description has been limited to single elements only for ease of explanation.
Although the present invention has been described in the above with reference to specific embodiments, it should be noted that various changes and modifications to the embodiments may be envisaged, which fall within the scope claimed for the invention as set out in the appended claims. The above specification should therefore be interpreted in a descriptive and not in a limiting sense.
Claims (18)
1. A method of manufacturing a thin-film diode, comprising the steps of:
(a) forming a first metallic layer upon an electrically insulating substrate;
(b) forming over said first metallic layer a layer of semiconductor material having a successively layered PIN internal structure;
(c) simultaneously patterning said first metallic layer and said semiconductor layer to form an elongated two-layer strip comprising an elongated metallic strip constituting a lower electrode, formed from said first metallic layer, and an elongated portion of said semiconductor layer formed on said lower electrode, the outer surface of said two-layer strip thereby comprising an upper face of said elongated semiconductor layer portion and side faces of said elongated semiconductor layer portion and said lower electrode;;
(d) forming a film of insulating material over said two-layer strip and surrounding surface areas of said substrate;
(e) removing said insulating film from said upper face of the elongated semiconductor layer portion, while leaving said side faces of the elongated semiconductor layer portion and lower electrode covered by said insulating film; and
(f) forming a second metallic layer over the previously formed layers, and patterning said second metallic layer to form an upper electrode comprising an elongated strip disposed to intersect and cover a portion of said elongated semiconductor layer portion upper face;
said thin-film diode being thereby formed by a portion of said semiconductor layer sandwiched between mutually overlapping opposed portions of said upper electrode and lower electrode, and by said mutually overlapping opposed electrode portions.
2. A method of manufacturing a thin-film diode according to claim 1, in which said step (f) of forming said upper electrode is followed by a further step of performing etching to remove all portions of said elongated semiconductor layer portion other than a portion thereof lying directly below said second electrode, utilizing said second electrode as a mask for said etching.
3. A method of manufacturing a thin-film diode according to claim 1, in which said step (f) of forming said upper electrode is preceded by a step of etching said elongated semiconductor layer portion to form a shortened portion thereof of predetermined length as measured along the direction of elongation of the lower electrode, said insulating film being left covering the side faces of said shortened semiconductor layer portion, and in which said upper electrode is positioned during said step (f) such as to lie across the upper face of said shortened semiconductor layer portion while being separated from the side faces thereof and the underlying portion of said lower electrode by said insulating film, with the length of said shortened semiconductor layer portion being set at a value at least equal to the width of said upper electrode plus a value of alignment tolerance for said patterning said upper electrode.
4. A method of manufacturing a thin-film diode according to claim 2 or claim 3, in which etching of said semiconductor layer is performed by anisotropic reactive ion beam etching.
5. A method of manufacturing a thin-film diode according to claim 1, in which said substrate is formed of an optically transparent material, and in which said step (e) of removing said insulating film portion comprises the steps of:
forming a layer of photo-sensitive etching resist material over said insulating film;
illuminating the opposite face of said substrate to that on which said insulating film is formed;
developing said etching resist layer; and
performing etching to remove a portion of said etching resist layer disposed above said insulating film over said elongated semiconductor layer portion, which has been shielded from said illumination, and to remove a corresponding portion of the insulating film lying on said elongated semiconductor layer portion upper face.
6. A method of manufacturing a thin-film diode according to claim 1, in which said step (e) of removing said insulating film portion from the upper face of said elongated semiconductor layer portion is performed by reactive ion beam etching of said insulating film.
7. A method of manufacturing a thin-film diode according to claim 1, in whih said step (c) of patterning said first metallic layer and said semiconductor layer is performed by photo-lithographic etching, whereby a layer of each resist material remains upon said upper face of said elongated semiconductor layer portion upon completion of said patterning, and further whereby said insulating film formed in said step (d) of claim 1 is formed over said resist layer, and whereby said resist layer is removed preceding removal of said insulating film over said semiconductor layer upper face, in step (e) of claim 1.
8. A method of manufacturing a thin-film diode according to claim 1, in which said semiconductor material is amorphous silicon.
9. A method of forming a thin-film diode according to claim 1, in which said insulating film comprises Si02.
10. A method of forming a thin-film diode according to claim 1, in which said lower electrode comprises successively deposited layers of InO3:Sn and Cr, and in which said upper electrode comprises successively deposited layers of Cr and Al.
11. A structure for a thin-film diode comprising:
a lower electrode comprising an elongated strip of metallic material formed on an electrically insulating substrate;
a layer of amorphous silicon having a successively layered PIN internal configuration formed upon said lower electrode, the width of said amorphous silicon layer being substantially identical to that of said lower electrode;
portions of an insulating film disposed to completely cover the side faces of said amorphous silicon layer and lower electrode which extend along the direction of elongation of said lower electrode; and
an upper electrode comprising an elongated strip of metallic material disposed such as to intersect the direction of elongation of said lower electrode substantially perpendicularly and to substantially cover and contact the upper face of said layer of amorphous silicon and to be insulated from said side faces of the lower electrode and amorphouse silicon layer by said insulating film portion.
12. A construction for a thin-film diode according to claim 11, and further comprising an intermediate layer formed between said amorphouse silicon layer and at least one of said upper and lower electrodes.
13. A construction for a thin-film diode according to claim 12, in which said intermediate layer is formed from at least one on a group of materials including Cr, Al and Mo.
14. A method of manufacturing a diode ring element formed of two thin-film diodes connected in parallel with opposing directions of conduction, comprising the steps of:
(a) forming a first metallic layer upon an electrically insulating substrate;
(b) forming over said first metallic layer a layer of semiconductor material having a successively layered PIN internal structure;;
(c) simultaneously patterning said first metallic layer and said semiconductor layer to form first and second elongated two-layer strips each comprising a substantially linearly elongated metallic strip constituting a lower electrode, formed from said first metallic layer, and an elongated portion of said semiconductor layer formed on said lower electrode, the outer surfacer of each of said two-layer strips thereby comprising an upper face of said elongated semiconductor layer portion and side faces of said elongated semiconductor layer portion and lower electrode thereof, said first and second two-layer strips being disposed adjacent and parallel to one another;
(d) forming a film of insulating material over said two-layer strips and surrounding surface areas of said substrate;;
(e) performing etching to remove said insulating film from said upper faces of said elongated semiconductor layer portions, while leaving said side faces of said elongated semiconductor layer portions and lower electrodes covered by said insulating film;
(f) performing etching of said first elongated semiconductor layer portion to remove portions thereof extending in the direction of elongation thereof on either side of a first shortened semiconductor layer portion of predetermined length, as measured along said direction of elongation,to thereby produce exposed portions of the corresponding lower electrode on either side of said first rectangular semiconductor layer portion, and performing etching of said second elongated semiconductor layer portion to remove portions thereof extending in the direction of elongation thereof on either side of a second shortened semiconductor layer portion of equal length to said first rectangular semiconductor layer portion, to thereby produce exposed portions of the corresponding lower electrode on either side of said second shortened semiconductor layer portion, said first and second shortened semiconductor layer portions being mutually offset with respect to said direction of elongation by an amount at least equal to said predetermined length thereof;
(g) forming a second layer of metallic material over said shortened semiconductor layer portions and surrounding areas of said insulating film and exposed portions of said lower electrodes;;
(h) performing patterning of said second metallic layer to form a pair of second electrodes, each being of substantially linear elongated shaped and having a width which is less than said predetermined length of said shortened semiconductor layer portions by an amount at least equal to an alignment tolerance value of said patterning to be allowed along the direction of elongation of said lower electrodes and aligned to intersect the direction of elongation of said lower electrodes substantially perpendicularly, with a first one of said upper electrodes being disposed such as to lie across said first shortened semiconductor layer portion and an exposed portion of the lower electrode of said second shortened semiconductor layer portion to provide electrical interconnection therebetween, and with a second one of said upper electrodes being disposed such as to lie across said second shortened semiconductor layer portion and an exposed portion of the lower electrode of said first shortened semiconductor layer portion, to provide electrical interconnection therebetween.
15. A method of manufacturing a diode ring element according to claim 14, in which said semiconductor material is amorphous silicon.
16. A method of manufacturing a thin film diode substantially as hereinbefore described with referenceto Figures3to7and 10to 13 of the accompanying drawings.
17. A structure for a thin film diode substantially as hereinbefore described with reference to Figures 3 to 7 and 10to 13 of the accompanying drawings.
18. A method of manufacturing a diode ring element substantially as hereinbefore described with reference to Figures 3 to 7 and 10 to 13 of the accompanying drawings.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58117488A JPH0652794B2 (en) | 1983-06-29 | 1983-06-29 | Method of manufacturing thin film diode |
| JP58122205A JPS6014468A (en) | 1983-07-05 | 1983-07-05 | Thin film diode |
| JP58136162A JPS6028276A (en) | 1983-07-26 | 1983-07-26 | Manufacture of thin film diode |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8416632D0 GB8416632D0 (en) | 1984-08-01 |
| GB2144266A true GB2144266A (en) | 1985-02-27 |
| GB2144266B GB2144266B (en) | 1987-03-18 |
Family
ID=27313386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08416632A Expired GB2144266B (en) | 1983-06-29 | 1984-06-29 | Method of manufacture for ultra-miniature thin-film diodes |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE3424085A1 (en) |
| FR (1) | FR2548450B1 (en) |
| GB (1) | GB2144266B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4732873A (en) * | 1985-04-02 | 1988-03-22 | Thomson-Csf | Method of fabrication of non-linear control elements for a flat electrooptical display screen |
| DE4410799A1 (en) * | 1994-03-29 | 1995-10-05 | Forschungszentrum Juelich Gmbh | diode |
| GB2305003A (en) * | 1995-08-23 | 1997-03-26 | Toshiba Cambridge Res Center | Semiconductor contact layer structure |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2579809B1 (en) * | 1985-04-02 | 1987-05-15 | Thomson Csf | METHOD FOR PRODUCING DIE-CONTROLLED DIES FOR ELECTRO-OPTICAL DISPLAY FLAT SCREEN AND FLAT SCREEN PRODUCED BY THIS PROCESS |
| FR2581781B1 (en) * | 1985-05-07 | 1987-06-12 | Thomson Csf | NON-LINEAR CONTROL ELEMENTS FOR FLAT ELECTROOPTIC DISPLAY SCREEN AND MANUFACTURING METHOD THEREOF |
| NL8702490A (en) * | 1987-10-19 | 1989-05-16 | Philips Nv | DISPLAY WITH LATERAL SCHOTTKY DIODS. |
| NL8802409A (en) * | 1988-09-30 | 1990-04-17 | Philips Nv | DISPLAY DEVICE, SUPPORT PLATE PROVIDED WITH DIODE AND SUITABLE FOR THE DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SUPPORT PLATE. |
| FR2714765B1 (en) * | 1993-12-30 | 1996-02-02 | France Telecom | Method of making an electrical connection between two conductive layers. |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4174217A (en) * | 1974-08-02 | 1979-11-13 | Rca Corporation | Method for making semiconductor structure |
| US4425379A (en) * | 1981-02-11 | 1984-01-10 | Fairchild Camera & Instrument Corporation | Polycrystalline silicon Schottky diode array |
| EP0071244B1 (en) * | 1981-07-27 | 1988-11-23 | Kabushiki Kaisha Toshiba | Thin-film transistor and method of manufacture therefor |
| US4642620A (en) * | 1982-09-27 | 1987-02-10 | Citizen Watch Company Limited | Matrix display device |
-
1984
- 1984-06-29 DE DE19843424085 patent/DE3424085A1/en active Granted
- 1984-06-29 FR FR8410296A patent/FR2548450B1/en not_active Expired
- 1984-06-29 GB GB08416632A patent/GB2144266B/en not_active Expired
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4732873A (en) * | 1985-04-02 | 1988-03-22 | Thomson-Csf | Method of fabrication of non-linear control elements for a flat electrooptical display screen |
| DE4410799A1 (en) * | 1994-03-29 | 1995-10-05 | Forschungszentrum Juelich Gmbh | diode |
| GB2305003A (en) * | 1995-08-23 | 1997-03-26 | Toshiba Cambridge Res Center | Semiconductor contact layer structure |
| GB2305003B (en) * | 1995-08-23 | 1997-10-08 | Toshiba Cambridge Res Center | Semiconductor contact layer structure |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2144266B (en) | 1987-03-18 |
| FR2548450A1 (en) | 1985-01-04 |
| GB8416632D0 (en) | 1984-08-01 |
| FR2548450B1 (en) | 1987-04-30 |
| DE3424085C2 (en) | 1989-05-03 |
| DE3424085A1 (en) | 1985-01-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6800872B2 (en) | Active matrix thin film transistor | |
| US6809785B2 (en) | Semipermeable liquid crystal display device and manufacturing method thereof | |
| US5926235A (en) | Active matrix liquid crystal display and method of making | |
| EP0449123B1 (en) | Liquid crystal display device | |
| US4960719A (en) | Method for producing amorphous silicon thin film transistor array substrate | |
| US7763490B2 (en) | Thin film transistor substrate and method for fabricating the same | |
| JP2003140189A (en) | Array substrate for liquid crystal display device and its manufacturing method | |
| US5834328A (en) | Method for fabricating liquid crystal display | |
| KR100322970B1 (en) | Method for manufacturing fringe field switching mode lcd | |
| JP2002303877A (en) | Array substrate for liquid crystal display device and method for manufacturing it | |
| KR100325072B1 (en) | Manufacturing method of high opening rate and high transmittance liquid crystal display device | |
| EP0556904B1 (en) | Method of fabricating thin film structures | |
| US5818551A (en) | Thin film transistor-liquid crystal display having patterned amorphous silicon and N+ amorphous layers and a manufacturing method therefor | |
| KR100356113B1 (en) | Method of manufacturing a liquid crystal display | |
| GB2144266A (en) | Method of manufacture for ultra-miniature thin-film diodes | |
| JPS6349914B2 (en) | ||
| JPH0684946A (en) | Active matrix liquid crystal display device and manufacture thereof | |
| JP2850564B2 (en) | Thin film transistor matrix and method of manufacturing the same | |
| KR20020056110A (en) | array panel of liquid crystal display device and manufacturing method thereof | |
| KR100268105B1 (en) | Thin-film transistor substrate and manufacturing method thereof | |
| JPH1138437A (en) | Liquid crystal display device and its manufacture | |
| KR100205869B1 (en) | A stagged thin film transistor and a method of fabricating the same | |
| JP2629743B2 (en) | Method for manufacturing thin film transistor | |
| JPS61117521A (en) | Production of semiconductor device | |
| JPS61196281A (en) | Substrate for display unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19950629 |