DE3405621C2 - - Google Patents

Info

Publication number
DE3405621C2
DE3405621C2 DE3405621A DE3405621A DE3405621C2 DE 3405621 C2 DE3405621 C2 DE 3405621C2 DE 3405621 A DE3405621 A DE 3405621A DE 3405621 A DE3405621 A DE 3405621A DE 3405621 C2 DE3405621 C2 DE 3405621C2
Authority
DE
Germany
Prior art keywords
line
decoder
electrodes
node
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3405621A
Other languages
German (de)
English (en)
Other versions
DE3405621A1 (de
Inventor
Kazuhiro Shimotori
Kazuyasu Fujishima
Hideyuki Ozaki
Hideshi Itami Hyogo Jp Miyatake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3405621A1 publication Critical patent/DE3405621A1/de
Application granted granted Critical
Publication of DE3405621C2 publication Critical patent/DE3405621C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
DE19843405621 1983-02-17 1984-02-16 Halbleiter-speichereinrichtung Granted DE3405621A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58026458A JPS59151398A (ja) 1983-02-17 1983-02-17 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE3405621A1 DE3405621A1 (de) 1984-08-23
DE3405621C2 true DE3405621C2 (OSRAM) 1989-09-28

Family

ID=12194060

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19843405621 Granted DE3405621A1 (de) 1983-02-17 1984-02-16 Halbleiter-speichereinrichtung

Country Status (4)

Country Link
US (1) US4641286A (OSRAM)
JP (1) JPS59151398A (OSRAM)
DE (1) DE3405621A1 (OSRAM)
GB (1) GB2138185B (OSRAM)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60191500A (ja) * 1984-03-08 1985-09-28 Sharp Corp 冗長回路
JPS6199999A (ja) * 1984-10-19 1986-05-19 Hitachi Ltd 半導体記憶装置
US4654830A (en) * 1984-11-27 1987-03-31 Monolithic Memories, Inc. Method and structure for disabling and replacing defective memory in a PROM
FR2576132B1 (fr) * 1985-01-15 1990-06-29 Eurotechnique Sa Memoire en circuit integre
JPS6337899A (ja) * 1986-07-30 1988-02-18 Mitsubishi Electric Corp 半導体記憶装置
JP2695411B2 (ja) * 1986-11-29 1997-12-24 三菱電機株式会社 半導体記憶装置
JPH073754B2 (ja) * 1988-03-08 1995-01-18 三菱電機株式会社 半導体記憶装置
US5223735A (en) * 1988-09-30 1993-06-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device in which circuit functions can be remedied or changed and the method for producing the same
JP2547633B2 (ja) * 1989-05-09 1996-10-23 三菱電機株式会社 半導体記憶装置
US5289417A (en) * 1989-05-09 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with redundancy circuit
KR970000501B1 (en) * 1991-04-12 1997-01-13 Hyundai Electronics Ind Semiconductor memory device with redundancy confirmative circuit
US5446401A (en) * 1994-03-13 1995-08-29 Advanced Micro Devices, Inc. Synchronous dual word decoding using PLA
US5506518A (en) * 1994-09-20 1996-04-09 Xilinx, Inc. Antifuse-based programmable logic circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3755791A (en) * 1972-06-01 1973-08-28 Ibm Memory system with temporary or permanent substitution of cells for defective cells
FR2232256A5 (OSRAM) * 1973-05-29 1974-12-27 Labo Cent Telecommunicat
US4228528B2 (en) * 1979-02-09 1992-10-06 Memory with redundant rows and columns
DE3036869C2 (de) * 1979-10-01 1985-09-05 Hitachi, Ltd., Tokio/Tokyo Integrierte Halbleiterschaltung und Schaltkreisaktivierverfahren
JPS5928560Y2 (ja) * 1979-11-13 1984-08-17 富士通株式会社 冗長ビットを有する記憶装置
US4281398A (en) * 1980-02-12 1981-07-28 Mostek Corporation Block redundancy for memory array
US4489402A (en) * 1981-04-25 1984-12-18 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4462091A (en) * 1982-02-26 1984-07-24 International Business Machines Corporation Word group redundancy scheme
US4485459A (en) * 1982-09-20 1984-11-27 Fairchild Camera & Instrument Corp. Redundant columns for byte wide memories
US4494220A (en) * 1982-11-24 1985-01-15 At&T Bell Laboratories Folded bit line memory with one decoder per pair of spare rows

Also Published As

Publication number Publication date
GB2138185B (en) 1987-09-09
US4641286A (en) 1987-02-03
DE3405621A1 (de) 1984-08-23
GB8403945D0 (en) 1984-03-21
JPH0156478B2 (OSRAM) 1989-11-30
GB2138185A (en) 1984-10-17
JPS59151398A (ja) 1984-08-29

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Legal Events

Date Code Title Description
OM8 Search report available as to paragraph 43 lit. 1 sentence 1 patent law
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)