DE3313163A1 - Halbleiteranordnung und verfahren zu ihrer herstellung - Google Patents

Halbleiteranordnung und verfahren zu ihrer herstellung

Info

Publication number
DE3313163A1
DE3313163A1 DE19833313163 DE3313163A DE3313163A1 DE 3313163 A1 DE3313163 A1 DE 3313163A1 DE 19833313163 DE19833313163 DE 19833313163 DE 3313163 A DE3313163 A DE 3313163A DE 3313163 A1 DE3313163 A1 DE 3313163A1
Authority
DE
Germany
Prior art keywords
layer
semiconductor
yttrium
substrate
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19833313163
Other languages
German (de)
English (en)
Other versions
DE3313163C2 (cg-RX-API-DMAC10.html
Inventor
Junichi Yokohama Kanagawa Ohno
Takao Tokyo Ohta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of DE3313163A1 publication Critical patent/DE3313163A1/de
Application granted granted Critical
Publication of DE3313163C2 publication Critical patent/DE3313163C2/de
Granted legal-status Critical Current

Links

Classifications

    • H10P14/6322—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/03—Manufacture or treatment wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
    • H10P14/69396—
    • H10P30/209—
    • H10P90/1906—
    • H10W10/061—
    • H10W10/181—
    • H10P90/1912—
    • H10W10/012—
    • H10W10/13—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/077—Implantation of silicon on sapphire
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/097—Lattice strain and defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/15—Silicon on sapphire SOS

Landscapes

  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE19833313163 1982-04-12 1983-04-12 Halbleiteranordnung und verfahren zu ihrer herstellung Granted DE3313163A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57060536A JPS58176967A (ja) 1982-04-12 1982-04-12 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3313163A1 true DE3313163A1 (de) 1983-10-20
DE3313163C2 DE3313163C2 (cg-RX-API-DMAC10.html) 1987-07-30

Family

ID=13145117

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19833313163 Granted DE3313163A1 (de) 1982-04-12 1983-04-12 Halbleiteranordnung und verfahren zu ihrer herstellung

Country Status (4)

Country Link
US (1) US4494996A (cg-RX-API-DMAC10.html)
JP (1) JPS58176967A (cg-RX-API-DMAC10.html)
DE (1) DE3313163A1 (cg-RX-API-DMAC10.html)
FR (1) FR2525031B1 (cg-RX-API-DMAC10.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996010842A1 (en) * 1994-09-30 1996-04-11 Aktsionernoe Obschestvo Zakrytogo Tipa 'vl' Field-effect transistor of the metal-dielectric-semiconductor type

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USH569H (en) 1984-09-28 1989-01-03 Motorola Inc. Charge storage depletion region discharge protection
JPS62500340A (ja) * 1984-09-28 1987-02-05 モトロ−ラ・インコ−ポレ−テツド 電荷蓄積空乏領域放電保護装置及び方法
US4733482A (en) * 1987-04-07 1988-03-29 Hughes Microelectronics Limited EEPROM with metal doped insulator
US5024965A (en) * 1990-02-16 1991-06-18 Chang Chen Chi P Manufacturing high speed low leakage radiation hardened CMOS/SOI devices
US5643804A (en) 1993-05-21 1997-07-01 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a hybrid integrated circuit component having a laminated body
US7858459B2 (en) 2007-04-20 2010-12-28 Texas Instruments Incorporated Work function adjustment with the implant of lanthanides
US7807522B2 (en) * 2006-12-28 2010-10-05 Texas Instruments Incorporated Lanthanide series metal implant to control work function of metal gate electrodes

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6614657A (cg-RX-API-DMAC10.html) * 1966-02-11 1967-08-14
IT7826422A0 (it) * 1977-09-22 1978-08-02 Rca Corp Circuito integrato planare a silicio su zaffiro (sos) e metodo per la fabbricazione dello stesso.
JPS5721856B2 (en) * 1977-11-28 1982-05-10 Nippon Telegraph & Telephone Semiconductor and its manufacture
US4177084A (en) * 1978-06-09 1979-12-04 Hewlett-Packard Company Method for producing a low defect layer of silicon-on-sapphire wafer
US4178191A (en) * 1978-08-10 1979-12-11 Rca Corp. Process of making a planar MOS silicon-on-insulating substrate device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NICHTS-ERMITTELT *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996010842A1 (en) * 1994-09-30 1996-04-11 Aktsionernoe Obschestvo Zakrytogo Tipa 'vl' Field-effect transistor of the metal-dielectric-semiconductor type

Also Published As

Publication number Publication date
DE3313163C2 (cg-RX-API-DMAC10.html) 1987-07-30
JPS58176967A (ja) 1983-10-17
FR2525031A1 (fr) 1983-10-14
JPH0258786B2 (cg-RX-API-DMAC10.html) 1990-12-10
FR2525031B1 (fr) 1987-01-30
US4494996A (en) 1985-01-22

Similar Documents

Publication Publication Date Title
DE3219441C2 (cg-RX-API-DMAC10.html)
DE69504252T2 (de) Flache Grabenisolation mit dünner Nitridauskleidung
DE10214066B4 (de) Halbleiterbauelement mit retrogradem Dotierprofil in einem Kanalgebiet und Verfahren zur Herstellung desselben
DE102011123124B3 (de) SiC-Halbleitervorrichtung
DE3311635C2 (cg-RX-API-DMAC10.html)
DE60004722T2 (de) Verfahren zur Herstellung eines Gruppe III-Nitrid-Verbindungshalbleitersubstrats
EP0005166B1 (de) Verfahren zur Herstellung von Halbleiteranordnungen mit isolierten Bereichen aus polykristallinem Silicium und danach hergestellte Halbleiteranordnungen
DE2808257B2 (de) Halbleitervorrichtung und verfahren zu ihrer herstellung
DE4422957B4 (de) Isolierverfahren für eine Halbleitervorrichtung
DE2539073B2 (de) Feldeffekt-Transistor mit isolierter Gate-Elektrode und Verfahren zu dessen Herstellung
DE2641752A1 (de) Verfahren zur herstellung eines feldeffekttransistors
DE102019004466A1 (de) PROZESS ZUM BILDEN EINER ELEKTRONISCHEN VORRICHTUNG EINSCHLIEßLICH EINES ZUGANGSBEREICHS
DE3540422C2 (de) Verfahren zum Herstellen integrierter Strukturen mit nicht-flüchtigen Speicherzellen, die selbst-ausgerichtete Siliciumschichten und dazugehörige Transistoren aufweisen
DE2225374A1 (de) Halbleitervorrichtung und verfahren zu ihrer herstellung
DE2365056A1 (de) Verfahren zur herstellung von halbleitereinrichtungen unter oertlicher oxidation einer silicium-oberflaeche
DE3125064A1 (de) "verfahren zum herstellen eines integrierten schaltkreises"
EP0000545B1 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit Selbstjustierung
DE2808645A1 (de) Verfahren zum einstellen des leckstromes von sos-isolierschicht-feldeffekttransistoren
DE3313163A1 (de) Halbleiteranordnung und verfahren zu ihrer herstellung
DE2654979C3 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE1814747C2 (de) Verfahren zum Herstellen von Feldefekttransistoren
DE3540452C2 (de) Verfahren zur Herstellung eines Dünnschichttransistors
DE3000121A1 (de) Verfahren zur herstellung einer mos-halbleitereinrichtung mit selbstjustierten anschluessen
DE69025784T2 (de) Nichtflüchtige Speicher-Halbleiteranordnung
DE3007500A1 (de) Verfahren zum passivieren eines integrierten schaltkreises

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8128 New person/name/address of the agent

Representative=s name: HENKEL, G., DR.PHIL. FEILER, L., DR.RER.NAT. HAENZ

8127 New person/name/address of the applicant

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee