DE3172166D1 - Multilayer metal silicide interconnections for integrated circuits - Google Patents

Multilayer metal silicide interconnections for integrated circuits

Info

Publication number
DE3172166D1
DE3172166D1 DE8181401940T DE3172166T DE3172166D1 DE 3172166 D1 DE3172166 D1 DE 3172166D1 DE 8181401940 T DE8181401940 T DE 8181401940T DE 3172166 T DE3172166 T DE 3172166T DE 3172166 D1 DE3172166 D1 DE 3172166D1
Authority
DE
Germany
Prior art keywords
integrated circuits
metal silicide
multilayer metal
interconnections
silicide interconnections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181401940T
Other languages
English (en)
Inventor
William I Lehrer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Application granted granted Critical
Publication of DE3172166D1 publication Critical patent/DE3172166D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE8181401940T 1980-12-09 1981-12-07 Multilayer metal silicide interconnections for integrated circuits Expired DE3172166D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/214,615 US4398335A (en) 1980-12-09 1980-12-09 Multilayer metal silicide interconnections for integrated circuits

Publications (1)

Publication Number Publication Date
DE3172166D1 true DE3172166D1 (en) 1985-10-10

Family

ID=22799774

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181401940T Expired DE3172166D1 (en) 1980-12-09 1981-12-07 Multilayer metal silicide interconnections for integrated circuits

Country Status (4)

Country Link
US (1) US4398335A (de)
EP (1) EP0055161B1 (de)
JP (1) JPS57122540A (de)
DE (1) DE3172166D1 (de)

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JPS58137231A (ja) * 1982-02-09 1983-08-15 Nec Corp 集積回路装置
US4495512A (en) * 1982-06-07 1985-01-22 International Business Machines Corporation Self-aligned bipolar transistor with inverted polycide base contact
JPS59154040A (ja) * 1983-02-22 1984-09-03 Toshiba Corp 半導体装置の製造方法
FR2542922B1 (fr) * 1983-03-18 1986-05-02 Efcis Procede de fabrication de circuits integres a plusieurs couches metalliques d'interconnexion et circuit realise par ce procede
DE3314879A1 (de) * 1983-04-25 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von stabilen, niederohmigen kontakten in integrierten halbleiterschaltungen
JPS6037787A (ja) * 1983-08-11 1985-02-27 Nec Corp 半導体装置
JPS60116167A (ja) * 1983-11-29 1985-06-22 Toshiba Corp 半導体記憶装置及びその製造方法
US4581623A (en) * 1984-05-24 1986-04-08 Motorola, Inc. Interlayer contact for use in a static RAM cell
JPS6185843A (ja) * 1984-10-04 1986-05-01 Nec Corp 半導体装置
US4604789A (en) * 1985-01-31 1986-08-12 Inmos Corporation Process for fabricating polysilicon resistor in polycide line
FR2578272B1 (fr) * 1985-03-01 1987-05-22 Centre Nat Rech Scient Procede de formation sur un substrat d'une couche de siliciure de tungstene, utilisable notamment pour la realisation de couches d'interconnexion des circuits integres.
US4920071A (en) * 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
JPS61256718A (ja) * 1985-05-10 1986-11-14 Nec Corp 半導体集積回路装置の製造方法
IT1186485B (it) * 1985-12-20 1987-11-26 Sgs Microelettronica Spa Circuito integrato monolitico,in particolare di tipo mos o cmos e processo per la realizzazione di tale circuito
US5266829A (en) * 1986-05-09 1993-11-30 Actel Corporation Electrically-programmable low-impedance anti-fuse element
US4823181A (en) * 1986-05-09 1989-04-18 Actel Corporation Programmable low impedance anti-fuse element
US4747211A (en) * 1987-02-09 1988-05-31 Sheldahl, Inc. Method and apparatus for preparing conductive screened through holes employing metallic plated polymer thick films
KR900008868B1 (ko) * 1987-09-30 1990-12-11 삼성전자 주식회사 저항성 접촉을 갖는 반도체 장치의 제조방법
US4962414A (en) * 1988-02-11 1990-10-09 Sgs-Thomson Microelectronics, Inc. Method for forming a contact VIA
US4971929A (en) * 1988-06-30 1990-11-20 Microwave Modules & Devices, Inc. Method of making RF transistor employing dual metallization with self-aligned first metal
JP2769331B2 (ja) * 1988-09-12 1998-06-25 株式会社日立製作所 半導体集積回路の製造方法
US5175118A (en) * 1988-09-20 1992-12-29 Mitsubishi Denki Kabushiki Kaisha Multiple layer electrode structure for semiconductor device and method of manufacturing thereof
JPH0728040B2 (ja) * 1988-09-20 1995-03-29 三菱電機株式会社 半導体装置およびその製造方法
IT1225623B (it) * 1988-10-20 1990-11-22 Sgs Thomson Microelectronics Formazione di contatti autoallineati senza l'impiego di una relativa maschera
JPH02285638A (ja) * 1989-04-27 1990-11-22 Toshiba Corp 半導体装置
US5102827A (en) * 1989-05-31 1992-04-07 At&T Bell Laboratories Contact metallization of semiconductor integrated-circuit devices
US5055901A (en) * 1989-08-08 1991-10-08 Ford Aerospace Corporation Multi-layer metal silicide infrared detector
US5290727A (en) * 1990-03-05 1994-03-01 Vlsi Technology, Inc. Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors
US5151387A (en) * 1990-04-30 1992-09-29 Sgs-Thomson Microelectronics, Inc. Polycrystalline silicon contact structure
JPH0680638B2 (ja) * 1990-07-05 1994-10-12 株式会社東芝 半導体装置の製造方法
US5208170A (en) * 1991-09-18 1993-05-04 International Business Machines Corporation Method for fabricating bipolar and CMOS devices in integrated circuits using contact metallization for local interconnect and via landing
US5266156A (en) * 1992-06-25 1993-11-30 Digital Equipment Corporation Methods of forming a local interconnect and a high resistor polysilicon load by reacting cobalt with polysilicon
JPH06283612A (ja) * 1993-03-26 1994-10-07 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
US5485031A (en) * 1993-11-22 1996-01-16 Actel Corporation Antifuse structure suitable for VLSI application
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US5441914A (en) * 1994-05-02 1995-08-15 Motorola Inc. Method of forming conductive interconnect structure
US5661081A (en) * 1994-09-30 1997-08-26 United Microelectronics Corporation Method of bonding an aluminum wire to an intergrated circuit bond pad
KR0138308B1 (ko) 1994-12-14 1998-06-01 김광호 층간접촉구조 및 그 방법
US5789764A (en) * 1995-04-14 1998-08-04 Actel Corporation Antifuse with improved antifuse material
US6110822A (en) * 1998-03-25 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for forming a polysilicon-interconnect contact in a TFT-SRAM
US7125815B2 (en) * 2003-07-07 2006-10-24 Micron Technology, Inc. Methods of forming a phosphorous doped silicon dioxide comprising layer
US7510966B2 (en) * 2005-03-07 2009-03-31 Micron Technology, Inc. Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines
US7256141B1 (en) * 2005-05-24 2007-08-14 Advanced Micro Devices, Inc. Interface layer between dual polycrystalline silicon layers
US7767577B2 (en) * 2008-02-14 2010-08-03 Chartered Semiconductor Manufacturing, Ltd. Nested and isolated transistors with reduced impedance difference
US20160276156A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing process thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1399163A (en) * 1972-11-08 1975-06-25 Ferranti Ltd Methods of manufacturing semiconductor devices
US3881971A (en) * 1972-11-29 1975-05-06 Ibm Method for fabricating aluminum interconnection metallurgy system for silicon devices
US4152823A (en) * 1975-06-10 1979-05-08 Micro Power Systems High temperature refractory metal contact assembly and multiple layer interconnect structure
JPS6029221B2 (ja) * 1977-01-14 1985-07-09 株式会社東芝 半導体装置の製造方法
US4265935A (en) * 1977-04-28 1981-05-05 Micro Power Systems Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
JPS5427382A (en) * 1977-08-01 1979-03-01 Nec Corp Semiconductor integrated circuit device
US4128670A (en) * 1977-11-11 1978-12-05 International Business Machines Corporation Fabrication method for integrated circuits with polysilicon lines having low sheet resistance
JPS5487175A (en) * 1977-12-23 1979-07-11 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
JPS5575240A (en) * 1978-12-01 1980-06-06 Nec Corp Method of fabricating semiconductor device
US4276557A (en) * 1978-12-29 1981-06-30 Bell Telephone Laboratories, Incorporated Integrated semiconductor circuit structure and method for making it
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections

Also Published As

Publication number Publication date
JPH0219974B2 (de) 1990-05-07
EP0055161B1 (de) 1985-09-04
EP0055161A1 (de) 1982-06-30
US4398335A (en) 1983-08-16
JPS57122540A (en) 1982-07-30

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Legal Events

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8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

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