DE3171338D1 - Method of manufacturing a semiconductor device with polycrystalline semiconductor cum metal electrodes - Google Patents
Method of manufacturing a semiconductor device with polycrystalline semiconductor cum metal electrodesInfo
- Publication number
- DE3171338D1 DE3171338D1 DE8181305120T DE3171338T DE3171338D1 DE 3171338 D1 DE3171338 D1 DE 3171338D1 DE 8181305120 T DE8181305120 T DE 8181305120T DE 3171338 T DE3171338 T DE 3171338T DE 3171338 D1 DE3171338 D1 DE 3171338D1
- Authority
- DE
- Germany
- Prior art keywords
- cum
- manufacturing
- metal electrodes
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000002184 metal Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55151557A JPS5775453A (en) | 1980-10-29 | 1980-10-29 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3171338D1 true DE3171338D1 (en) | 1985-08-14 |
Family
ID=15521122
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8181305120T Expired DE3171338D1 (en) | 1980-10-29 | 1981-10-29 | Method of manufacturing a semiconductor device with polycrystalline semiconductor cum metal electrodes |
Country Status (4)
Country | Link |
---|---|
US (1) | US4497106A (de) |
EP (1) | EP0052450B1 (de) |
JP (1) | JPS5775453A (de) |
DE (1) | DE3171338D1 (de) |
Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL8104862A (nl) * | 1981-10-28 | 1983-05-16 | Philips Nv | Halfgeleiderinrichting, en werkwijze ter vervaardiging daarvan. |
JPS58225663A (ja) * | 1982-06-23 | 1983-12-27 | Toshiba Corp | 半導体装置の製造方法 |
DE3230077A1 (de) * | 1982-08-12 | 1984-02-16 | Siemens AG, 1000 Berlin und 8000 München | Integrierte bipolar- und mos-transistoren enthaltende halbleiterschaltung auf einem chip und verfahren zu ihrer herstellung |
JPS5931052A (ja) * | 1982-08-13 | 1984-02-18 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JPS5955052A (ja) * | 1982-09-24 | 1984-03-29 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JPS5987850A (ja) * | 1982-11-11 | 1984-05-21 | Matsushita Electronics Corp | 半導体装置 |
JPS5994861A (ja) * | 1982-11-24 | 1984-05-31 | Hitachi Ltd | 半導体集積回路装置及びその製造方法 |
EP0122313B1 (de) * | 1983-04-18 | 1987-01-07 | Deutsche ITT Industries GmbH | Verfahren zum Herstellen einer monolithisch integrierten Schaltung mit mindestens einem integrierten Isolierschicht-Feldeffekttransistor |
GB2143083B (en) * | 1983-07-06 | 1987-11-25 | Standard Telephones Cables Ltd | Semiconductor structures |
JPS6057952A (ja) * | 1983-09-09 | 1985-04-03 | Toshiba Corp | 半導体装置の製造方法 |
JPS6080267A (ja) * | 1983-10-07 | 1985-05-08 | Toshiba Corp | 半導体集積回路装置の製造方法 |
JPS60158655A (ja) * | 1984-01-27 | 1985-08-20 | Rohm Co Ltd | 半導体装置およびその製造方法 |
JPH0691197B2 (ja) * | 1984-02-08 | 1994-11-14 | 株式会社日立製作所 | 半導体集積回路装置 |
US5280188A (en) * | 1985-03-07 | 1994-01-18 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and a plurality of MOS transistors |
US5340762A (en) * | 1985-04-01 | 1994-08-23 | Fairchild Semiconductor Corporation | Method of making small contactless RAM cell |
US5100824A (en) * | 1985-04-01 | 1992-03-31 | National Semiconductor Corporation | Method of making small contactless RAM cell |
CA1258320A (en) * | 1985-04-01 | 1989-08-08 | Madhukar B. Vora | Small contactless ram cell |
JPS61287159A (ja) * | 1985-06-13 | 1986-12-17 | Oki Electric Ind Co Ltd | Bi−CMOS半導体IC装置の製造方法 |
US5324982A (en) * | 1985-09-25 | 1994-06-28 | Hitachi, Ltd. | Semiconductor memory device having bipolar transistor and structure to avoid soft error |
US6740958B2 (en) | 1985-09-25 | 2004-05-25 | Renesas Technology Corp. | Semiconductor memory device |
NL8600770A (nl) * | 1986-03-26 | 1987-10-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
JP2515745B2 (ja) * | 1986-07-14 | 1996-07-10 | 株式会社日立製作所 | 半導体装置の製造方法 |
GB2193036B (en) * | 1986-07-24 | 1990-05-02 | Mitsubishi Electric Corp | Method of fabricating a semiconductor integrated circuit device |
EP0272433B1 (de) * | 1986-11-18 | 1993-03-31 | Siemens Aktiengesellschaft | Integrierte Halbleiterschaltung mit als Dünnschichtstege auf den die aktiven Transistorbereiche trennenden Feldoxidbereichen angeordneten Lastwiderstände und Verfahren zu ihrer Herstellung |
JP2538600B2 (ja) * | 1987-07-23 | 1996-09-25 | 富士通株式会社 | 半導体装置の製造方法 |
US4980303A (en) * | 1987-08-19 | 1990-12-25 | Fujitsu Limited | Manufacturing method of a Bi-MIS semiconductor device |
KR900001062B1 (ko) * | 1987-09-15 | 1990-02-26 | 강진구 | 반도체 바이 씨 모오스 장치의 제조방법 |
US5121185A (en) * | 1987-10-09 | 1992-06-09 | Hitachi, Ltd. | Monolithic semiconductor IC device including blocks having different functions with different breakdown voltages |
US4994887A (en) * | 1987-11-13 | 1991-02-19 | Texas Instruments Incorporated | High voltage merged bipolar/CMOS technology |
US5001081A (en) * | 1988-01-19 | 1991-03-19 | National Semiconductor Corp. | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide |
US5179031A (en) * | 1988-01-19 | 1993-01-12 | National Semiconductor Corporation | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide |
US5124817A (en) * | 1988-01-19 | 1992-06-23 | National Semiconductor Corporation | Polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide |
JPH01255264A (ja) * | 1988-04-05 | 1989-10-12 | Seiko Instr Inc | 半導体装置の製造方法 |
DE3914910C2 (de) * | 1988-05-10 | 1999-11-25 | Northern Telecom Ltd | Verfahren zur Herstellung einer integrierten Schaltung |
GB8810973D0 (en) * | 1988-05-10 | 1988-06-15 | Stc Plc | Improvements in integrated circuits |
US5008208A (en) * | 1988-12-07 | 1991-04-16 | Honeywell Inc. | Method of making planarized, self-aligned bipolar integrated circuits |
JP2787921B2 (ja) * | 1989-01-06 | 1998-08-20 | 三菱電機株式会社 | 絶縁ゲート型バイポーラトランジスタ |
JP3024143B2 (ja) * | 1989-06-19 | 2000-03-21 | ソニー株式会社 | 半導体装置の製法 |
US4960726A (en) * | 1989-10-19 | 1990-10-02 | International Business Machines Corporation | BiCMOS process |
US5082796A (en) * | 1990-07-24 | 1992-01-21 | National Semiconductor Corporation | Use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers |
JPH04237160A (ja) * | 1991-01-22 | 1992-08-25 | Nec Corp | バイポーラcmos複合型半導体装置 |
KR0138352B1 (ko) * | 1993-12-17 | 1998-04-28 | 김광호 | 반도체 장치 및 그의 제조방법 |
US5454258A (en) * | 1994-05-09 | 1995-10-03 | Olin Corporation | Broad range moisture analyzer and method |
KR0161378B1 (ko) * | 1994-06-13 | 1998-12-01 | 김광호 | 바이폴라 접합 트랜지스터 제조방법 |
US5556796A (en) * | 1995-04-25 | 1996-09-17 | Micrel, Inc. | Self-alignment technique for forming junction isolation and wells |
US5668037A (en) * | 1995-10-06 | 1997-09-16 | Micron Technology, Inc. | Method of forming a resistor and integrated circuitry having a resistor construction |
JP2865045B2 (ja) * | 1996-02-28 | 1999-03-08 | 日本電気株式会社 | 半導体装置の製造方法 |
US5923078A (en) * | 1996-07-11 | 1999-07-13 | Micron Technology, Inc. | Method of forming a resistor and integrated circuitry having a resistor construction |
US6130137A (en) * | 1997-10-20 | 2000-10-10 | Micron Technology, Inc. | Method of forming a resistor and integrated circuitry having a resistor construction |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51127682A (en) * | 1975-04-30 | 1976-11-06 | Fujitsu Ltd | Manufacturing process of semiconductor device |
JPS5921191B2 (ja) * | 1975-06-14 | 1984-05-18 | 富士通株式会社 | 電界効果半導体装置の製造方法 |
US4120707A (en) * | 1977-03-30 | 1978-10-17 | Harris Corporation | Process of fabricating junction isolated IGFET and bipolar transistor integrated circuit by diffusion |
JPS5846863B2 (ja) * | 1977-08-25 | 1983-10-19 | 松下電器産業株式会社 | 半導体集積回路装置 |
JPS5485680A (en) * | 1977-12-21 | 1979-07-07 | Toshiba Corp | Semiconductor device and its manufacture |
-
1980
- 1980-10-29 JP JP55151557A patent/JPS5775453A/ja active Pending
-
1981
- 1981-10-28 US US06/315,903 patent/US4497106A/en not_active Expired - Lifetime
- 1981-10-29 EP EP81305120A patent/EP0052450B1/de not_active Expired
- 1981-10-29 DE DE8181305120T patent/DE3171338D1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0052450B1 (de) | 1985-07-10 |
US4497106A (en) | 1985-02-05 |
JPS5775453A (en) | 1982-05-12 |
EP0052450A1 (de) | 1982-05-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |