DE2905675C2 - - Google Patents
Info
- Publication number
- DE2905675C2 DE2905675C2 DE2905675A DE2905675A DE2905675C2 DE 2905675 C2 DE2905675 C2 DE 2905675C2 DE 2905675 A DE2905675 A DE 2905675A DE 2905675 A DE2905675 A DE 2905675A DE 2905675 C2 DE2905675 C2 DE 2905675C2
- Authority
- DE
- Germany
- Prior art keywords
- gate
- memory
- signal
- input
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 claims description 81
- 230000008859 change Effects 0.000 claims description 7
- 230000004913 activation Effects 0.000 description 23
- 239000000872 buffer Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000002146 bilateral effect Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Microcomputers (AREA)
- Read Only Memory (AREA)
- Power Sources (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/884,790 US4145761A (en) | 1978-03-09 | 1978-03-09 | Ram retention during power up and power down |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE2905675A1 DE2905675A1 (de) | 1979-09-20 |
| DE2905675C2 true DE2905675C2 (US06521211-20030218-C00004.png) | 1988-12-01 |
Family
ID=25385398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19792905675 Granted DE2905675A1 (de) | 1978-03-09 | 1979-02-14 | Schaltungsanordnung zur sperrung des zugangs zu einem speicher |
Country Status (7)
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4453068A (en) * | 1979-05-01 | 1984-06-05 | Rangaire Corporation | Induction cook-top system and control |
| CA1160744A (en) * | 1979-05-09 | 1984-01-17 | Jesse T. Quatse | Electronic postage meter having improved security and fault tolerance features |
| US4484307A (en) * | 1979-05-09 | 1984-11-20 | F.M.E. Corporation | Electronic postage meter having improved security and fault tolerance features |
| US4247913A (en) * | 1979-05-10 | 1981-01-27 | Hiniker Company | Protection circuit for storage of volatile data |
| US4271487A (en) * | 1979-11-13 | 1981-06-02 | Ncr Corporation | Static volatile/non-volatile ram cell |
| US4288865A (en) * | 1980-02-06 | 1981-09-08 | Mostek Corporation | Low-power battery backup circuit for semiconductor memory |
| US4322807A (en) * | 1980-03-07 | 1982-03-30 | The Perkin-Elmer Corporation | Safe memory system for a spectrophotometer |
| US4327410A (en) * | 1980-03-26 | 1982-04-27 | Ncr Corporation | Processor auto-recovery system |
| US4323987A (en) * | 1980-03-28 | 1982-04-06 | Pitney Bowes Inc. | Power failure memory support system |
| JPS6022438B2 (ja) * | 1980-05-06 | 1985-06-01 | 松下電器産業株式会社 | 不揮発性メモリのリフレッシュ方式 |
| JPS5764397A (en) * | 1980-10-03 | 1982-04-19 | Olympus Optical Co Ltd | Memory device |
| JPS5769588A (en) * | 1980-10-16 | 1982-04-28 | Nec Corp | Memort circuit |
| US4388706A (en) * | 1980-12-01 | 1983-06-14 | General Electric Company | Memory protection arrangement |
| JPH0124656Y2 (US06521211-20030218-C00004.png) * | 1981-05-18 | 1989-07-26 | ||
| JPS5875264A (ja) * | 1981-10-29 | 1983-05-06 | Mitsubishi Electric Corp | マイクロプロセツサ |
| US4578774A (en) * | 1983-07-18 | 1986-03-25 | Pitney Bowes Inc. | System for limiting access to non-volatile memory in electronic postage meters |
| FR2571870B1 (fr) * | 1984-10-15 | 1987-02-20 | Sagem | Dispositif de sauvegarde de memoire de microprocesseur. |
| JPS61125660A (ja) * | 1984-11-22 | 1986-06-13 | Toshiba Corp | バツテリ−バツクアツプ回路 |
| JP3172214B2 (ja) * | 1991-09-30 | 2001-06-04 | 富士通株式会社 | 状態モード設定方式 |
| US5935253A (en) * | 1991-10-17 | 1999-08-10 | Intel Corporation | Method and apparatus for powering down an integrated circuit having a core that operates at a speed greater than the bus frequency |
| US5682471A (en) * | 1994-10-06 | 1997-10-28 | Billings; Thomas Neal | System for transparently storing inputs to non-volatile storage and automatically re-entering them to reconstruct work if volatile memory is lost |
| US5802132A (en) * | 1995-12-29 | 1998-09-01 | Intel Corporation | Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme |
| US5834956A (en) | 1995-12-29 | 1998-11-10 | Intel Corporation | Core clock correction in a 2/N mode clocking scheme |
| US5884084A (en) * | 1996-10-31 | 1999-03-16 | Intel Corporation | Circuit and method for using early reset to prevent CMOS corruption with advanced power supplies |
| JPH10254587A (ja) * | 1997-03-14 | 1998-09-25 | Toshiba Corp | コンピュータシステム |
| US5986962A (en) * | 1998-07-23 | 1999-11-16 | International Business Machines Corporation | Internal shadow latch |
| JP2000114935A (ja) | 1998-10-02 | 2000-04-21 | Nec Corp | 順序回路 |
| US7259654B2 (en) | 2000-02-28 | 2007-08-21 | Magellan Technology Pty Limited | Radio frequency identification transponder |
| US7248145B2 (en) * | 2000-02-28 | 2007-07-24 | Magellan Technology Oty Limited | Radio frequency identification transponder |
| KR100560665B1 (ko) * | 2003-07-02 | 2006-03-16 | 삼성전자주식회사 | 독출 방지 기능을 갖는 반도체 메모리 장치 |
| EP2319043B1 (en) | 2008-07-21 | 2018-08-15 | Sato Holdings Corporation | A device having data storage |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1440099A (fr) * | 1965-04-15 | 1966-05-27 | Labo Cent Telecommunicat | Perfectionnements aux mémoires à lecture destructive fonctionnant en mémoires semi-permanentes |
| US3680061A (en) * | 1970-04-30 | 1972-07-25 | Ncr Co | Integrated circuit bipolar random access memory system with low stand-by power consumption |
| DE2121865C3 (de) * | 1971-05-04 | 1983-12-22 | Ibm Deutschland Gmbh, 7000 Stuttgart | Speicher-Adressierschaltung |
| US4082966A (en) * | 1976-12-27 | 1978-04-04 | Texas Instruments Incorporated | Mos detector or sensing circuit |
-
1978
- 1978-03-09 US US05/884,790 patent/US4145761A/en not_active Expired - Lifetime
- 1978-12-12 GB GB7848115A patent/GB2016179B/en not_active Expired
-
1979
- 1979-01-31 FR FR7902569A patent/FR2419545A1/fr active Granted
- 1979-02-14 DE DE19792905675 patent/DE2905675A1/de active Granted
- 1979-03-01 JP JP2404179A patent/JPS54124942A/ja active Pending
-
1984
- 1984-02-23 SG SG163/84A patent/SG16384G/en unknown
-
1985
- 1985-01-21 JP JP1985006693U patent/JPS60150700U/ja active Granted
- 1985-12-30 MY MY471/85A patent/MY8500471A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| MY8500471A (en) | 1985-12-31 |
| GB2016179A (en) | 1979-09-19 |
| SG16384G (en) | 1985-02-15 |
| GB2016179B (en) | 1982-11-03 |
| FR2419545A1 (fr) | 1979-10-05 |
| FR2419545B1 (US06521211-20030218-C00004.png) | 1983-09-09 |
| DE2905675A1 (de) | 1979-09-20 |
| JPS6324505Y2 (US06521211-20030218-C00004.png) | 1988-07-05 |
| JPS54124942A (en) | 1979-09-28 |
| US4145761A (en) | 1979-03-20 |
| JPS60150700U (ja) | 1985-10-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8110 | Request for examination paragraph 44 | ||
| D2 | Grant after examination | ||
| 8363 | Opposition against the patent | ||
| 8331 | Complete revocation |