DE2832012A1 - Verfahren zum herstellen einer dreidimensionalen integrierten schaltung - Google Patents

Verfahren zum herstellen einer dreidimensionalen integrierten schaltung

Info

Publication number
DE2832012A1
DE2832012A1 DE19782832012 DE2832012A DE2832012A1 DE 2832012 A1 DE2832012 A1 DE 2832012A1 DE 19782832012 DE19782832012 DE 19782832012 DE 2832012 A DE2832012 A DE 2832012A DE 2832012 A1 DE2832012 A1 DE 2832012A1
Authority
DE
Germany
Prior art keywords
doping
integrated circuit
semiconductor body
dimensional integrated
epitaxially grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19782832012
Other languages
German (de)
English (en)
Other versions
DE2832012C2 (enrdf_load_stackoverflow
Inventor
Gerhard Krause
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Priority to DE19782832012 priority Critical patent/DE2832012A1/de
Publication of DE2832012A1 publication Critical patent/DE2832012A1/de
Application granted granted Critical
Publication of DE2832012C2 publication Critical patent/DE2832012C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)
DE19782832012 1978-07-20 1978-07-20 Verfahren zum herstellen einer dreidimensionalen integrierten schaltung Granted DE2832012A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19782832012 DE2832012A1 (de) 1978-07-20 1978-07-20 Verfahren zum herstellen einer dreidimensionalen integrierten schaltung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19782832012 DE2832012A1 (de) 1978-07-20 1978-07-20 Verfahren zum herstellen einer dreidimensionalen integrierten schaltung

Publications (2)

Publication Number Publication Date
DE2832012A1 true DE2832012A1 (de) 1980-01-31
DE2832012C2 DE2832012C2 (enrdf_load_stackoverflow) 1987-11-12

Family

ID=6044956

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19782832012 Granted DE2832012A1 (de) 1978-07-20 1978-07-20 Verfahren zum herstellen einer dreidimensionalen integrierten schaltung

Country Status (1)

Country Link
DE (1) DE2832012A1 (enrdf_load_stackoverflow)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076101A3 (en) * 1981-09-25 1984-09-05 Kabushiki Kaisha Toshiba Stacked semiconductor device
WO1985002493A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company FABRICATION OF InP CONTAINING SEMICONDUCTOR DEVICES HAVING HIGH AND LOW RESISTIVITY REGIONS
WO1985002495A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company Fabrication of group iii-v compound semiconductor devices having high and low resistivity regions
WO1985002496A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company METHOD OF FABRICATING AlGaAs SEMICONDUCTOR DEVICES HAVING HIGH AND LOW RESISTIVITY REGIONS
EP0208294A1 (en) * 1985-07-11 1987-01-14 Nec Corporation Three-dimensional integrated circuit
DE3743776A1 (de) * 1987-12-23 1989-07-13 Licentia Gmbh Vergrabene halbleiterbauelemente und verfahren zu deren herstellung

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1514854A1 (de) * 1964-08-18 1969-08-21 Texas Instruments Inc Monolithische elektrische Anordnung und Verfahren zu ihrer Herstellung
US3564358A (en) * 1967-11-15 1971-02-16 Siemens Ag Integrated circuit structure containing multiple sandwich layers of monocrystalline semiconductor and insulator material

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1514854A1 (de) * 1964-08-18 1969-08-21 Texas Instruments Inc Monolithische elektrische Anordnung und Verfahren zu ihrer Herstellung
US3564358A (en) * 1967-11-15 1971-02-16 Siemens Ag Integrated circuit structure containing multiple sandwich layers of monocrystalline semiconductor and insulator material

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076101A3 (en) * 1981-09-25 1984-09-05 Kabushiki Kaisha Toshiba Stacked semiconductor device
US4569700A (en) * 1981-09-25 1986-02-11 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a stacked semiconductor device
WO1985002493A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company FABRICATION OF InP CONTAINING SEMICONDUCTOR DEVICES HAVING HIGH AND LOW RESISTIVITY REGIONS
WO1985002495A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company Fabrication of group iii-v compound semiconductor devices having high and low resistivity regions
WO1985002496A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company METHOD OF FABRICATING AlGaAs SEMICONDUCTOR DEVICES HAVING HIGH AND LOW RESISTIVITY REGIONS
EP0208294A1 (en) * 1985-07-11 1987-01-14 Nec Corporation Three-dimensional integrated circuit
DE3743776A1 (de) * 1987-12-23 1989-07-13 Licentia Gmbh Vergrabene halbleiterbauelemente und verfahren zu deren herstellung

Also Published As

Publication number Publication date
DE2832012C2 (enrdf_load_stackoverflow) 1987-11-12

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8125 Change of the main classification

Ipc: H01L 21/72

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee