DE2832012A1 - Three=dimensional integrated circuit prodn. - has epitaxially grown substrate with components produced by alternate doping - Google Patents

Three=dimensional integrated circuit prodn. - has epitaxially grown substrate with components produced by alternate doping

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Publication number
DE2832012A1
DE2832012A1 DE19782832012 DE2832012A DE2832012A1 DE 2832012 A1 DE2832012 A1 DE 2832012A1 DE 19782832012 DE19782832012 DE 19782832012 DE 2832012 A DE2832012 A DE 2832012A DE 2832012 A1 DE2832012 A1 DE 2832012A1
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Prior art keywords
doping
integrated circuit
semiconductor body
dimensional integrated
epitaxially grown
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Granted
Application number
DE19782832012
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German (de)
Other versions
DE2832012C2 (en
Inventor
Gerhard Krause
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Siemens AG
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Siemens AG
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Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19782832012 priority Critical patent/DE2832012A1/en
Publication of DE2832012A1 publication Critical patent/DE2832012A1/en
Application granted granted Critical
Publication of DE2832012C2 publication Critical patent/DE2832012C2/de
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

The integrated circuit consists of an epitaxially grown semiconductor substrate, contg. elements produced by doping, both on its surface and inside. The epitaxial and doping steps are alternated, in order to obtain a high precision for positioning the individual elements, as well as good reproducibility of the individual doping gradients. Pref. the alternating epitaxially and doping steps are separated by an interval of approx. one min. The doping is typically ion implantation in structured steps, typically controlled by a computer. In such instance an ion-optical mask is used. A temp. gradient may be generated orthogonally to the treated substrate surface which thus becomes hotter than the other one.

Description

Verfahren zum Herstellen einer dreidimensionalenMethod of making a three-dimensional

integrierten Schaltung Die Erfindung betrifft ein Verfahren zum Herstellen einer dreidimensionalen integrierten Schaltung aus einem durch Epitaxie aufgebauten Halbleiterkörper, der durch Dotierung erzeugte Bauelemente an seiner Oberfläche und in seinem Innern enthält.integrated circuit The invention relates to a method of manufacturing a three-dimensional integrated circuit from a built up by epitaxy Semiconductor body, the components produced by doping on its surface and contained within.

Bekanntlich wird eine viel größere Packungsdichte in einer integrierten Schaltung erzielt, wenn die einzelnen Bauelemente nicht nur an der Oberfläche des Halbleiterkörpers, sondern auch in dessen Innern vorgesehen werden. Dadurch ist es möglich, die einzelnen Bauelemente und damit auch die einzelnen Funktionseinheiten in geringerer räumlicher Entfernung zueinander anzuordnen, so daß die Laufzeiten der Signale zwischen den einzelnen Funktionseinheiten wesentlich kürzer sind, was für sehr schnelle logische Schaltungen von besonderer Bedeutung ist.As is well known, a much greater packing density is integrated in an Circuit achieved when the individual components are not only on the surface of the Semiconductor body, but also be provided in its interior. This is it is possible to use the individual components and thus also the individual functional units to be arranged at a smaller spatial distance from one another, so that the running times the signals between the individual functional units are much shorter, what is of particular importance for very fast logic circuits.

Bei der Herstellung einer solchen integrierten Schaltung aus Galliumarsenid wird zunächst auf einem Galliumarsenid-Substrat durch Epitaxie eine Galliumarsenid-Schicht mit aktiven Bauelementen hergestellt. Auf dieser Galliumarsenid-Schicht wird anschließend eine semiisolierende Galliumarsenid-Schicht epitaktisch abgeschieden.When manufacturing such an integrated circuit from gallium arsenide First, a gallium arsenide layer is epitaxially applied to a gallium arsenide substrate manufactured with active components. On this gallium arsenide layer is then a semi-insulating gallium arsenide layer is epitaxially deposited.

In einer weiteren Galliumarsenid-Schicht werden sodann wiederum aktive Bauelemente erzeugt. Dieses Verfahren kann gegebenenfalls mehrmals wiederholt werden.In a further gallium arsenide layer they become active again Components generated. This procedure can be repeated several times if necessary.

Um das Kristallwachstum von Galliumarsenid nicht zu stören, werden die Verbindungsleitungen zwischen den einzelnen Bauelementen bevorzugt als hochdotierte Schichten verwirklicht. Die Leitfähigkeit dieser hochdotierten Schichten ist mindestens in lokalen Bereichen innerhalb einzelner Funktionseinheiten hierfür ausreichend.In order not to disturb the crystal growth of gallium arsenide the connecting lines between the individual components are preferably highly doped Layers realized. The conductivity of these highly doped layers is at least sufficient for this in local areas within individual functional units.

Gegebenenfalls können auch metallische Leiterbahnen, die möglichst schmal sind, für die Verbindungsleitungen eingebaut werden. Bei geeigneter thermischer Behandlung werden diese metallischen Leiterbahnen von der Seite her einkristallin überwachsen, wenn die nächste epitaktische Schicht aufgetragen wird.If necessary, metallic conductor tracks can also be used are narrow, for which connecting lines are installed. With suitable thermal Treatment, these metallic conductor tracks become monocrystalline from the side overgrown when the next epitaxial layer is applied.

Außer horizontalen Leiterbahnen sind bei einer dreidimensionalen integrierten Schaltung gewöhnlich auch vertikale Verbindungsleitungen erforderlich. Diese können durch lokale Dotierung oder durch Öffnen von Löchern und Füllen der Löcher mit einem Leiter oder durch Thermomigration hergestellt werden.Besides horizontal conductor tracks are integrated into a three-dimensional one Switching usually also requires vertical interconnects. these can by local doping or by opening holes and filling the holes with one Conductor or by thermomigration.

Bei Halbleitermaterialien mit großem Bandabstand können anstelle der semiisolierenden Schichten auch vollisolierende Schichten verwendet werden, wie zum Beispiel Siliciumdioxid.In the case of semiconductor materials with a large band gap, instead of the semi-insulating layers can also be used as fully insulating layers for example silicon dioxide.

Es ist Aufgabe der Erfindung, ein Verfahren der eingangs genannten Art anzugeben, das insbesondere für aus Galliumarsenid bestehende Halbleiterkörper geeignet ist und auf besonders einfache Art die Herstellung einer dreidimensionalen integrierten Schaltung ermöglicht.It is the object of the invention to provide a method of the type mentioned at the beginning Specify type, in particular for semiconductor bodies made of gallium arsenide is suitable and in a particularly simple way the production of a three-dimensional integrated circuit enables.

Diese Aufgabe wird erfindungsgemäß dadurch gelöst, daß Epitaxie und Dotierung abwechselnd erfolgen.This object is achieved according to the invention in that epitaxy and Doping take place alternately.

Bei der Erfindung wird also wechselweise, insbesondere in einem zeitlichen Abstand von etwa einer Minute, der Halbleiterkörper epitaktisch aufgebaut und die Dotierung vorgenommen. Dadurch ist eine genaue Anordnung der einzelnen Bauelemente im- Halbleiterkörper gewährleistet, während gleichzeitig die gewünschten Dotierungskonzentrationen mit hoher Reproduzierbarkeit eingestellt werden können.In the invention, therefore, alternately, in particular in a temporal manner Distance of about one minute, the semiconductor body built up epitaxially and the Doping made. This ensures a precise arrangement of the individual components in the semiconductor body ensures, while at the same time the desired doping concentrations can be adjusted with high reproducibility.

Nachfolgend wird ein Ausführungsbeispiel der Erfindung naher erläutert: Auf einem halbisolierenden Galliumarsenid-Substrat wird wechselweise in einem zeitlichen Abstand von etwa einer Minute eine Galliumarsenid-Schicht epitaktisch aufgebaut und die Dotierung durch Implantation oder Aufdampfen vorgenommen. Das epitaktische Abscheiden erfolgt dabei im Dampfstrahl oder durch Abscheiden aus einer Verbindung. Während des Dotierungsabschnittes wird der Gasstrom für das epitaktische Abscheiden durch ein Ventil unterbrochen. Das epitaktische Abscheiden und die Dotierung erfolgen vorzugsweise in einem mit einer Vakuumpumpe verbundenen Reaktor.An exemplary embodiment of the invention is explained in more detail below: On a semi-insulating gallium arsenide substrate is alternated in a temporal A gallium arsenide layer is epitaxially built up about one minute apart and the doping is carried out by implantation or vapor deposition. The epitaxial Deposition takes place in a steam jet or by deposition from a compound. During the doping section, the gas flow is used for epitaxial deposition interrupted by a valve. The epitaxial deposition and the doping take place preferably in a reactor connected to a vacuum pump.

Während des Dotierungsabschnittes wird die Dotierungsstruktur der gesamten Halbleiteroberfläche, die gerade aufgebaut wird, erzeugt. Dies ist durch rechnergesteuerte Ionenimplantation, durch ionenoptische Abbildung einer Maske in die Ebene der Halbleiteroberfläche oder durch Einfügen einer Maske kurz vor der Halbleiteroberfläche möglich.During the doping section, the doping structure becomes the entire semiconductor surface that is straight is built, generated. This is through computer-controlled ion implantation, through ion-optical imaging a mask in the plane of the semiconductor surface or by inserting a mask possible shortly before the semiconductor surface.

Es hat sich gezeigt, daß bei der Herstellung vielschichtiger Strukturen die zuerst hergestellten epitaktischen Schichten bei den folgenden Prozeßschritten und insbesondere bei Anwendung herkömmlicher epitaktischer Verfahren stark ausdiffundieren.It has been shown that in the manufacture of multi-layered structures the epitaxial layers produced first in the following process steps and especially when conventional epitaxial processes are used, they diffuse out considerably.

Daher wird im Halbleiterkörper senkrecht zur behandelten Oberfläche ein Temperaturgradient eingestellt. Die Unterseite des Halbleiterkörpers wird hierzu durch Beru~hrung mit einer Metallfläche auf einer Temperatur gehalten, die zum Beispiel 300 0C unterhalb der Temperatur der gegenüberliegenden Oberfläche liegt. Diese gegenüberliegende oder freie Oberfläche wird hierzu mit einer starken Lichtquelle aufgeheizt.Therefore, the semiconductor body is perpendicular to the treated surface a temperature gradient is set. The underside of the semiconductor body is used for this kept at a temperature by contact with a metal surface, for example 300 0C below the temperature of the opposite surface. This opposite or the free surface is heated up with a strong light source.

Da im Laufe des Herstellungsverfahrens der Wärmewiderstand des Halbleiterkörpers ansteigt, wird die Temperatur der Halbleiterkörper-Unterseite nach einem vorgegebenen Programm während der Herstellung verringert.Because in the course of the manufacturing process the thermal resistance of the semiconductor body increases, the temperature of the semiconductor body underside according to a predetermined Program decreased during manufacture.

Die freie Oberfläche wird weiterhin einer starken W-Strahlung ausgesetzt. Hierzu kann auch die oben erläuterte starke Lichtquelle dienen. Hierdurch kann die 0 Oberflächentemperatur um etwa weitere 50 C gesenkt werden. Außerdem ist es möglich, die freie Oberfläche durch Elektronen aufzuheizen. In diesem Fall ist die direkte nichtthermische Anregung besonders stark, so daß mit sehr geringen Epitaxietemperaturen gearbeitet werden kann.The free surface continues to be exposed to strong UV radiation. The strong light source explained above can also be used for this purpose. This allows the 0 surface temperature can be reduced by about another 50 C. It is also possible to heat the free surface with electrons. In this case the direct one nonthermal excitation particularly strong, so that with very low epitaxial temperatures can be worked.

Großflächige Schichten ohne besondere Strukturen können gleichzeitig mit der Epitaxie dotiert werden. Schließlich ist es auch möglich, die Oberfläche des Halbleiterkörpers während des epitaktischen Prozesses periodisch impulsförmig aufzuheizen, und zwar mit einer Impulsdauer im Bereich von /us.Large-area layers without special structures can be used at the same time be doped with the epitaxy. Finally, it is also possible to use the surface of the semiconductor body periodically pulse-shaped during the epitaxial process to heat up, with a pulse duration in the range of / us.

7 Patentansprüche7 claims

Claims (7)

Patentansprüche @ Verfahren zum Herstellen einer dreidimensionalen integrierten Schaltung aus einem durch Epitaxie aufgebauten Halbleiterkörper, der durch Dotierung erzeugte Bauelemente an seiner Oberfläche und in seinem Innern enthält, d a d u r c h g e k e n n z e i c h n e t daß Epitaxie und Dotierung abwechselnd erfolgen. Claims @ Method for producing a three-dimensional integrated circuit from a semiconductor body built up by epitaxy, the contains components produced by doping on its surface and inside, d a d u r c h e k e n n n z e i c h n e t that epitaxy and doping alternate take place. 2. Verfahren nach Anspruch 1, d a d u r c h g e -k e n n z e i c h n e t , daß Epitaxie und Dotierung in einem zeitlichen Abstand von ca. einer Minute erfolgen 2. The method of claim 1, d a d u r c h g e -k e n n z e i c h n e t that epitaxy and doping occur at a time interval of about one minute take place 3. Verfahren nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß die Dotierung durch Ionenimplantation erfolgt.3. The method according to claim 1 or 2, d a d u r c h g e k e n n z e i c It should be noted that the doping is carried out by ion implantation. 4. Verfahren nach Anspruch 3, d a d u r c h g e -k e n n z e i c h n e t , daß die Ionenimplantation strukturiert vorgenommen wird.4. The method according to claim 3, d a d u r c h g e -k e n n z e i c h n e t that the ion implantation is carried out in a structured manner. 5. Verfahren nach Anspruch 4, d a d u r c h g e -k e n n z e i c h n e t , daß die Strukturierung durch rechnergesteuerte Ionenimplantation, durch ionenoptische Abbildung einer Maske in die Halbleiterkörper-Oberfläche oder durch Einfügen einer Maske kurz vor der Halbleiterkörper-Oberfläche erfolgt.5. The method according to claim 4, d a d u r c h g e -k e n n z e i c h n e t that the structuring by computer-controlled ion implantation, by ion-optical imaging of a mask in the semiconductor body surface or through A mask is inserted shortly before the surface of the semiconductor body. 6. Verfahren nach einem der Ansprüche 1 bis 5, d a -d u r c h g e k e n n z e i c h n e t , daß im Halbleiterkörper ein Temperaturgradient senkrecht zur behandelten Oberfläche erzeugt wird, so daß diese Oberfläche eine höhere Temperatur als die gegenüberliegende Oberfläche aufweist.6. The method according to any one of claims 1 to 5, d a -d u r c h g e It is not possible to say that a temperature gradient is perpendicular in the semiconductor body to the treated surface is generated, so that this surface has a higher temperature than the opposite surface. 7. Verfahren nach Anspruch 6, d a d u r c h g e -k e n n z e i c h n e t , daß die Temperatur der gegenüberliegenden Oberfläche fortschreitend nach einem vorbestimmten Programm abgesenkt wird.7. The method according to claim 6, d a d u r c h g e -k e n n z e i c h n e t that the temperature of the opposite surface is progressively increasing a predetermined program is lowered.
DE19782832012 1978-07-20 1978-07-20 Three=dimensional integrated circuit prodn. - has epitaxially grown substrate with components produced by alternate doping Granted DE2832012A1 (en)

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DE19782832012 DE2832012A1 (en) 1978-07-20 1978-07-20 Three=dimensional integrated circuit prodn. - has epitaxially grown substrate with components produced by alternate doping

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DE2832012A1 true DE2832012A1 (en) 1980-01-31
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076101A2 (en) * 1981-09-25 1983-04-06 Kabushiki Kaisha Toshiba Methode of manufacturing a stacked semiconductor device
WO1985002495A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company Fabrication of group iii-v compound semiconductor devices having high and low resistivity regions
WO1985002493A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company FABRICATION OF InP CONTAINING SEMICONDUCTOR DEVICES HAVING HIGH AND LOW RESISTIVITY REGIONS
WO1985002496A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company METHOD OF FABRICATING AlGaAs SEMICONDUCTOR DEVICES HAVING HIGH AND LOW RESISTIVITY REGIONS
EP0208294A1 (en) * 1985-07-11 1987-01-14 Nec Corporation Three-dimensional integrated circuit
DE3743776A1 (en) * 1987-12-23 1989-07-13 Licentia Gmbh Buried semiconductor components and method for their production

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1514854A1 (en) * 1964-08-18 1969-08-21 Texas Instruments Inc Monolithic electrical assembly and method of making it
US3564358A (en) * 1967-11-15 1971-02-16 Siemens Ag Integrated circuit structure containing multiple sandwich layers of monocrystalline semiconductor and insulator material

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1514854A1 (en) * 1964-08-18 1969-08-21 Texas Instruments Inc Monolithic electrical assembly and method of making it
US3564358A (en) * 1967-11-15 1971-02-16 Siemens Ag Integrated circuit structure containing multiple sandwich layers of monocrystalline semiconductor and insulator material

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076101A2 (en) * 1981-09-25 1983-04-06 Kabushiki Kaisha Toshiba Methode of manufacturing a stacked semiconductor device
EP0076101A3 (en) * 1981-09-25 1984-09-05 Kabushiki Kaisha Toshiba Stacked semiconductor device
US4569700A (en) * 1981-09-25 1986-02-11 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a stacked semiconductor device
WO1985002495A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company Fabrication of group iii-v compound semiconductor devices having high and low resistivity regions
WO1985002493A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company FABRICATION OF InP CONTAINING SEMICONDUCTOR DEVICES HAVING HIGH AND LOW RESISTIVITY REGIONS
WO1985002496A1 (en) * 1983-11-28 1985-06-06 American Telephone & Telegraph Company METHOD OF FABRICATING AlGaAs SEMICONDUCTOR DEVICES HAVING HIGH AND LOW RESISTIVITY REGIONS
EP0208294A1 (en) * 1985-07-11 1987-01-14 Nec Corporation Three-dimensional integrated circuit
DE3743776A1 (en) * 1987-12-23 1989-07-13 Licentia Gmbh Buried semiconductor components and method for their production

Also Published As

Publication number Publication date
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