DE2659200C2 - Prüfanordnung für einen Fehlererkennungskreis in einer Datenverarbeitungsschaltung - Google Patents

Prüfanordnung für einen Fehlererkennungskreis in einer Datenverarbeitungsschaltung

Info

Publication number
DE2659200C2
DE2659200C2 DE2659200A DE2659200A DE2659200C2 DE 2659200 C2 DE2659200 C2 DE 2659200C2 DE 2659200 A DE2659200 A DE 2659200A DE 2659200 A DE2659200 A DE 2659200A DE 2659200 C2 DE2659200 C2 DE 2659200C2
Authority
DE
Germany
Prior art keywords
parity
shift register
data
detection circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2659200A
Other languages
German (de)
English (en)
Other versions
DE2659200A1 (de
Inventor
Yasuo Dipl.-Ing. Kawasaki Kanagawa Kurihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE2659200A1 publication Critical patent/DE2659200A1/de
Application granted granted Critical
Publication of DE2659200C2 publication Critical patent/DE2659200C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Probability & Statistics with Applications (AREA)
  • Detection And Correction Of Errors (AREA)
DE2659200A 1975-12-30 1976-12-28 Prüfanordnung für einen Fehlererkennungskreis in einer Datenverarbeitungsschaltung Expired DE2659200C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15811975A JPS5283046A (en) 1975-12-30 1975-12-30 Check system of error detection circuit

Publications (2)

Publication Number Publication Date
DE2659200A1 DE2659200A1 (de) 1977-07-21
DE2659200C2 true DE2659200C2 (de) 1982-06-03

Family

ID=15664704

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2659200A Expired DE2659200C2 (de) 1975-12-30 1976-12-28 Prüfanordnung für einen Fehlererkennungskreis in einer Datenverarbeitungsschaltung

Country Status (5)

Country Link
US (1) US4107649A (cg-RX-API-DMAC10.html)
JP (1) JPS5283046A (cg-RX-API-DMAC10.html)
DE (1) DE2659200C2 (cg-RX-API-DMAC10.html)
FR (1) FR2337375A1 (cg-RX-API-DMAC10.html)
GB (1) GB1566309A (cg-RX-API-DMAC10.html)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1148900B (it) * 1980-09-05 1986-12-03 Sits Soc It Telecom Siemens Disposizione circuitale atta a rilevare la presenza di malfunzionamenti degli organi preposti al trasferimento diretto di dati in un sistema utilizzante un microprocessore di tipo commerciale
US4441182A (en) * 1981-05-15 1984-04-03 Rockwell International Corporation Repetitious logic state signal generation apparatus
US4398233A (en) * 1982-03-03 1983-08-09 Electronics Corporation Of America Fail-safe device for electronic control circuit
US4574343A (en) * 1982-09-29 1986-03-04 Kabushiki Kaisha Komatsu Seisakusho Contactless press control device
NL8302722A (nl) * 1983-08-01 1985-03-01 Philips Nv Inrichting voor het bewaken van de telfunctie van tellers.
US4878168A (en) * 1984-03-30 1989-10-31 International Business Machines Corporation Bidirectional serial test bus device adapted for control processing unit using parallel information transfer bus
US4670876A (en) * 1985-05-15 1987-06-02 Honeywell Inc. Parity integrity check logic
GB2179179B (en) * 1985-08-12 1989-10-18 British Gas Corp Improvements in or relating to burner control systems
JPH0756503B2 (ja) * 1985-11-26 1995-06-14 株式会社日立製作所 論理回路診断方法
JPS63102517A (ja) * 1986-10-20 1988-05-07 Nec Corp 機器障害信号伝送方式
US4740968A (en) * 1986-10-27 1988-04-26 International Business Machines Corporation ECC circuit failure detector/quick word verifier
DE3771663D1 (de) * 1986-10-31 1991-08-29 Siemens Ag Verfahren zur paritaetsbitermittlung und zur ueberwachung der uebertragung beim datenschieben sowie schaltungsanordnung zur durchfuehrung der verfahren.
GB2200476B (en) * 1987-01-29 1991-02-06 British Gas Plc Monitor system
US4884273A (en) * 1987-02-03 1989-11-28 Siemens Aktiengesellschaft Method and apparatus for monitoring the consistency of successive binary code signal groups in data processing equipment
EP0294505B1 (en) * 1987-06-11 1993-03-03 International Business Machines Corporation Clock generator system
US5195093A (en) * 1991-02-14 1993-03-16 Motorola, Inc. Method and apparatus for ensuring CRC error generation by a data communication station experiencing transmitter exceptions
US5276690A (en) * 1992-01-30 1994-01-04 Intel Corporation Apparatus utilizing dual compare logic for self checking of functional redundancy check (FRC) logic
US5440604A (en) * 1994-04-26 1995-08-08 Unisys Corporation Counter malfunction detection using prior, current and predicted parity
KR100346123B1 (ko) * 1999-12-29 2002-08-01 삼성전자 주식회사 데이터 통신 시스템에서 패러티 검사 장치 및 방법
US7020811B2 (en) * 2001-04-24 2006-03-28 Sun Microsystems, Inc. System and method for verifying error detection/correction logic
EP1435005B1 (en) * 2001-06-01 2005-12-14 Koninklijke Philips Electronics N.V. A digital system and a method for error detection thereof
JP2006242569A (ja) * 2005-02-28 2006-09-14 Advantest Corp 試験装置、及び試験方法
JP5179726B2 (ja) * 2006-06-27 2013-04-10 マーベル ワールド トレード リミテッド 半導体デバイス
CN102541719A (zh) * 2010-12-24 2012-07-04 鸿富锦精密工业（深圳）有限公司 排除错误观测值的系统及方法
US11374576B1 (en) * 2020-12-30 2022-06-28 Texas Instruments Incorporated Self-diagnostic counter

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3119098A (en) * 1960-10-31 1964-01-21 Ibm Stream editing unit
US3342983A (en) * 1963-06-25 1967-09-19 Ibm Parity checking and parity generating means for binary adders
US3562711A (en) * 1968-07-16 1971-02-09 Ibm Apparatus for detecting circuit malfunctions
US3567916A (en) * 1969-01-22 1971-03-02 Us Army Apparatus for parity checking a binary register
US3911261A (en) * 1974-09-09 1975-10-07 Ibm Parity prediction and checking network

Also Published As

Publication number Publication date
GB1566309A (en) 1980-04-30
FR2337375A1 (fr) 1977-07-29
DE2659200A1 (de) 1977-07-21
JPS5283046A (en) 1977-07-11
FR2337375B1 (cg-RX-API-DMAC10.html) 1980-09-12
US4107649A (en) 1978-08-15
JPS5540894B2 (cg-RX-API-DMAC10.html) 1980-10-21

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Legal Events

Date Code Title Description
D2 Grant after examination
8328 Change in the person/name/address of the agent

Free format text: REINLAENDER, C., DIPL.-ING. DR.-ING., PAT.-ANW., 8000 MUENCHEN

8339 Ceased/non-payment of the annual fee