DE2643609C2 - - Google Patents

Info

Publication number
DE2643609C2
DE2643609C2 DE19762643609 DE2643609A DE2643609C2 DE 2643609 C2 DE2643609 C2 DE 2643609C2 DE 19762643609 DE19762643609 DE 19762643609 DE 2643609 A DE2643609 A DE 2643609A DE 2643609 C2 DE2643609 C2 DE 2643609C2
Authority
DE
Germany
Prior art keywords
gate
input
signal
binary
half adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE19762643609
Other languages
German (de)
English (en)
Other versions
DE2643609A1 (de
Inventor
Homer W. Peoria Ariz. Us Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Bull Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Bull Inc filed Critical Honeywell Bull Inc
Publication of DE2643609A1 publication Critical patent/DE2643609A1/de
Application granted granted Critical
Publication of DE2643609C2 publication Critical patent/DE2643609C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/502—Half adders; Full adders consisting of two cascaded half adders
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4806—Cascode or current mode logic

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
DE19762643609 1975-10-01 1976-09-28 Aus zwei halbaddierern aufgebauter uebertragsfehlersicherer volladdierer in cml-technik Granted DE2643609A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US61870975A 1975-10-01 1975-10-01

Publications (2)

Publication Number Publication Date
DE2643609A1 DE2643609A1 (de) 1977-04-14
DE2643609C2 true DE2643609C2 (enExample) 1988-09-22

Family

ID=24478821

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19762643609 Granted DE2643609A1 (de) 1975-10-01 1976-09-28 Aus zwei halbaddierern aufgebauter uebertragsfehlersicherer volladdierer in cml-technik

Country Status (7)

Country Link
JP (1) JPS5926056B2 (enExample)
AU (1) AU1821276A (enExample)
BE (1) BE846854A (enExample)
CA (1) CA1076706A (enExample)
DE (1) DE2643609A1 (enExample)
FR (1) FR2326739A1 (enExample)
GB (1) GB1521790A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4215418A (en) * 1978-06-30 1980-07-29 Trw Inc. Integrated digital multiplier circuit using current mode logic

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3519810A (en) * 1967-02-14 1970-07-07 Motorola Inc Logic element (full adder) using transistor tree-like configuration
US3978329A (en) * 1975-09-12 1976-08-31 Bell Telephone Laboratories, Incorporated One-bit full adder

Also Published As

Publication number Publication date
GB1521790A (en) 1978-08-16
JPS5244127A (en) 1977-04-06
CA1076706A (en) 1980-04-29
BE846854A (fr) 1977-01-31
DE2643609A1 (de) 1977-04-14
FR2326739A1 (fr) 1977-04-29
JPS5926056B2 (ja) 1984-06-23
AU1821276A (en) 1978-04-06

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8127 New person/name/address of the applicant

Owner name: HONEYWELL BULL INC., MINNEAPOLIS, MINN., US

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee