GB1521790A - Current mode half and full adders - Google Patents
Current mode half and full addersInfo
- Publication number
- GB1521790A GB1521790A GB4077976A GB4077976A GB1521790A GB 1521790 A GB1521790 A GB 1521790A GB 4077976 A GB4077976 A GB 4077976A GB 4077976 A GB4077976 A GB 4077976A GB 1521790 A GB1521790 A GB 1521790A
- Authority
- GB
- United Kingdom
- Prior art keywords
- gate
- transistor
- level logic
- output
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/502—Half adders; Full adders consisting of two cascaded half adders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
- G06F2207/4802—Special implementations
- G06F2207/4806—Cascode or current mode logic
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
1521790 Adders HONEYWELL INFORMATION SYSTEMS Inc 1 Oct 1976 [1 Oct 1975] 40779/76 Heading G4A In a current node logic half adder, first and second upper level logic gates 105, 110 (Fig. 1) receive a first reference voltage and one of the two input signals A, the first or second of the gates 105, 110 being fed with current in dependence on whether the other input signal B, which is fed to a low level logic gate 120, is "1" or "0" respectively. The sum output is obtained by combining the outputs representing #A.B from the first gate and A.#B from the second gate in an OR gate 115, the carry signal being the output representing A.B from the first gate. The two half adders 100,200 may be combined to provide a full adder, the first receiving the inputs A and B and the second receiving the sum output from the first and the carry input, with the sum output being the sum from the second half adder 200 and the carry output being derived by ORing the carriers from both half adders. The low level logic gate 120 is formed by a transistor pair Q 4 , Q 6 (Fig. 4) with their emitters connected, the transistor Q 4 receiving the second input signal B via an emitter follower Q 2 , transistor Q 8 dropping the voltage of the first reference voltage by the same amount. Constant current for the gate is provided by transistor Q 5 . Each of the higher level logic gates 105, 110 comprises a similar transistor pair with the reference voltage being fed direct to the base of one transistor and the first input signal A being connected to the base of the other transistor.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US61870975A | 1975-10-01 | 1975-10-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1521790A true GB1521790A (en) | 1978-08-16 |
Family
ID=24478821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB4077976A Expired GB1521790A (en) | 1975-10-01 | 1976-10-01 | Current mode half and full adders |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS5926056B2 (en) |
| AU (1) | AU1821276A (en) |
| BE (1) | BE846854A (en) |
| CA (1) | CA1076706A (en) |
| DE (1) | DE2643609A1 (en) |
| FR (1) | FR2326739A1 (en) |
| GB (1) | GB1521790A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4215418A (en) * | 1978-06-30 | 1980-07-29 | Trw Inc. | Integrated digital multiplier circuit using current mode logic |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3519810A (en) * | 1967-02-14 | 1970-07-07 | Motorola Inc | Logic element (full adder) using transistor tree-like configuration |
| US3978329A (en) * | 1975-09-12 | 1976-08-31 | Bell Telephone Laboratories, Incorporated | One-bit full adder |
-
1976
- 1976-09-28 DE DE19762643609 patent/DE2643609A1/en active Granted
- 1976-09-29 AU AU18212/76A patent/AU1821276A/en not_active Expired
- 1976-09-30 JP JP11789376A patent/JPS5926056B2/en not_active Expired
- 1976-09-30 CA CA262,411A patent/CA1076706A/en not_active Expired
- 1976-09-30 FR FR7629471A patent/FR2326739A1/en not_active Withdrawn
- 1976-10-01 BE BE171165A patent/BE846854A/en not_active IP Right Cessation
- 1976-10-01 GB GB4077976A patent/GB1521790A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2643609C2 (en) | 1988-09-22 |
| BE846854A (en) | 1977-01-31 |
| JPS5244127A (en) | 1977-04-06 |
| FR2326739A1 (en) | 1977-04-29 |
| JPS5926056B2 (en) | 1984-06-23 |
| DE2643609A1 (en) | 1977-04-14 |
| CA1076706A (en) | 1980-04-29 |
| AU1821276A (en) | 1978-04-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |