GB1354040A - Analogue signal sorting circuit - Google Patents

Abstract

1354040 Arranging signals in order of magnitude INTERNATIONAL BUSINESS MACHINES CORP 29 Dec 1972 [14 Jan 1972] 60157/72 Heading H3T [Also in Division G4] A sorting circuit for sorting into order of magnitude a plurality of analogue signals comprises an analogue OR circuit for each order, each order OR circuit having inputs for receiving simultaneously all the analogue signals and an output for the largest signal of the order, and a switch for each analogue signal to each order analogue OR circuit except that of highest order, each of the switches operating to close the associated input when the associated analogue signal has been identified as the largest signal in a higher order analogue OR circuit. The arrangement is particularly intended for use in character recognition systems. Signals derived from N amplifiers, e.g. 10, 11, 12 are applied over lines 14, 15, 16 respectively to an OR gate comprising transistors 18, 19, 20 having a common emitter circuit resistor: the first largest signal appears in the collector circuit of the corresponding one of the transistors 18, 19, 20, e.g. transistor 18. The signals are also applied to a second OR circuit comprising transistors 30, 31, 32 via diode gates 40, 41, 42 respectively; one gate, e.g. 40 is however biased so that no signal reaches transistor 30 since the corresponding transistor 18 in the first OR circuit is conductive. The signals are further applied to a third OR circuit comprising transistors 50, 51, 52, each of which is again preceded by a diode gate 60, 61, 62 respectively so that no signal reaches a transistor when a corresponding transistor in a higher order OR circuit is conductive. A signal proportional to the difference between the largest input and next largest is obtained at terminal 91, by means of differential amplifier 90, which derives one input across resistor R4 and a second across resistor R8: an output is similarly derived at terminal 96 corresponding to the difference between the second and third largest inputs. The Specification also describes a modification in which the common emitter resistors R4, R8 &c. are replaced by current sources (Fig. 2, not shown) and also a modified diode gate circuit (Fig. 3, not shown).