US3714465A

US3714465A - Analog decision circuit

Info

Publication number: US3714465A
Application number: US00217770A
Authority: US
Inventors: D Skrenes
Original assignee: Individual
Current assignee: Individual
Priority date: 1972-01-14
Filing date: 1972-01-14
Publication date: 1973-01-30
Anticipated expiration: 1990-01-30
Also published as: FR2168109B1; DE2300725A1; JPS5535752B2; JPS4881570A; FR2168109A1; GB1354040A

Abstract

An analog decision circuit for analyzing a group of analog signals and identifying and ordering these signals according to their magnitudes. A first analog signal OR circuit identifies the largest magnitude analog signal and by means of a feedback circuit, this signal is eliminated from a second analog signal OR circuit which identifies the next largest analog signal. A second feedback circuit eliminates the second largest analog signal from the input of a third analog signal OR circuit which identifies the third largest analog signal. Similar circuitry is provided for each additional analog signal. Comparator circuits are also included to determine the separation between one largest analog signal and the next largest signal.

Description

United States Patent Skrenes 1 1 Jan. 30, 1973 [54] ANALOG DECISION CIRCUIT 3,593,285 7 1971 Gillmann ..307/235 R x 3,609,397 9/1971 Zaman ..307/235 R [76] lnventor. Davld Hans Skrenes, Route 1, 3,609,565 9H9. Arnold v y I 307/235 R X Byron 55920 3,646,457 2 1972 David et a1... ..307 235 R x [22] Fil 1 97z 3,678,5l3 7/l972 ward, .11. ..307/235 R X Appl. No.: 217,770

[56] References Cited UNITED STATES PATENTS 3,092,732 6/1963 Milford ..307/255 X 3,123,722 3/1964 Ralphs ..307/235 X 3,228,002 l/l966 Reines ..307/235 3,293,452 12/1966 Horwitz ..328/l16 X 3,358,157 12/1967 Shearme ..307/235 3,409,830 11/1968 Phillips, Jr ..328/l16 X 3,456,127 7/1969 Gray et a1. ..307/237 X 3,522,449 8/1970 McMurtrie ..307/235 Primary ExaminerHerman Karl Saalbach Assistant Examiner-L. N. Anagnos Att0rneyDonald F. Vosset al.

ABSTRACT gest analog signal from the input of a third analog 7 Claims, 3 Drawing Figures PATENTEB JAN 3 0 I973 SHEET 10F 6 PATENTEB Ma 01975 SHEET 2 OF 6 PATENTED JAN 3 01973 SHEET 5 OF 6 IIIIIIIIIIII ANALOG DECISION CIRCUIT BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to analog decision circuitry for analyzing relative magnitudes of analog signals and more particularly to analog decision circuitry for identifying the analog signal of a group of analog signals having the largest magnitude, ordering the analog signals according to their magnitudes, and finding the difference in magnitude between one analog signal and the next largest.

2. Description the Prior Art Circuits for detecting relative magnitudes of analog signals are well known in the prior art. U.S. Pat. No. 3,293,452, discloses a circuit which sequentially detects analog signals according to their magnitude in decreasing order. There is no provision for providing a simultaneous indication of the largest and next largest analog signal, and for finding the separation or difference in magnitude between these signals. A circuit for identifying one of a plurality of input signals that has the greatest voltage amplitude is set forth in U.S. Pat. No. 3,092,732. The circuit of this patent does not have a provision for ordering the analog signals according to their magnitude or for finding the difference in magnitude between the signal having the greatest voltage amplitude and the signal having the second greatest voltage amplitude. The lack of these features also exists in U.S. Pat. No. 3,593,285.

SUMMARY OF THE INVENTION The principal objects of the invention are to provide an improved analog decision circuit which a. simultaneously identifies analog signals of a group of analog signals according to their magnitudes;

b. simultaneously orders the analog signals of a group of analog signals according to their magnitude;

c. provides a separation signal indicating the difference between one analog signal and the next largest analog signal ofa group of analog signals, and

d. can identify analog signals of a group of analog signals according to their relative magnitudes and order the same at very high speed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic circuit diagram illustrating the invention;

FIG. 2 illustrates the current sources which would normally be used in place of the common resistor in the analogsignal OR circuits and FIG. 3 shows an alternate embodiment for the feedback switch between the cascaded analog signal OR circuits in FIG. 1.

DESCRIPTION computing systems and hybrid analog and digital computing systems. i

The inputs to the

correlation amplifiers

10, 11 and 12 are connected to various outputs of the scanner, not shown, in the character recognition system. Each of the correlation amplifiers is designed to recognize a particular character in response to the input signals from the scanner. Although each of the correlation amplifiers will have an output signal, the correlation amplifier having the largest output signal represents the identity of the character scanned. However, in order to have a valid or confident recognition or identification of the character scanned, it is desirable that the largest signal be a predetermined amount greater than the next largest signal. Therefore, in this invention, the signals from the correlation amplifiers are identified and sorted according to magnitude. Also, the difference between the largest and next largest signal is derived to facilitate a determination as to whether or not a valid and confident recognition has taken place.

The output of

correlation amplifiers

10, 11 and 12 are connected by

conductors

14, 15 and 16 to the bases of

transistors

18, 19 and 20, which have their emitters commonly connected to conductor 21.

Transistors

18, 19 and 20 are connected as an analog OR circuit. Resistors R1, R2, and R3 are connected in the collector circuits of

transistors

18, 19 and 20 respectively. Resistor R4 is connected to conductor 21 as a common emitter resistor. The first largest signal identification output terminals 26, 27 and 28 are connected to the collectors of

transistors

18, 19 and 20 respectively. Only one of these output terminals will have an identification signal identifying the largest output.

The next largest output signal is determined by an analog signal OR

circuit including transistors

30, 31 and 32. However, the inputs to the bases of these

transistors

30, 31 and 32 are applied to

diode switches

40, 41 and 42 respectively. The diode switches 40, 41 and 42 are controlled by

feedback circuits

44, 45 and 46 which are connected to the collectors of transistors l8, l9 and 20 respectively. The

feedback circuits

44, 45 and 46 have resistors R9, R10 and R11 connected between the collectors of transistors l8, l9 and 20 respectively, and the diodes forming the diode switch. Each of the

diode switches

40, 41 and 42 include a pair of diodes connected back to back. Resistors RI and diodes DI provide isolation in the feedback circuits.

The diode switches 40, 41 and 42 operate so as to remove the largest identified signal from the analog signal OR circuit formed by the

transistors

30, 31 and 32. This will be described in more detail shortly.

The nth largest signal is identified by the analog signal OR

circuit including transistors

50, 51 and 52. The bases of these

transistors

50, 51 and 52 are connected. to diode switches 60, 61 and 62 respectively. These diode switches are connected in a feedback circuit in the same manner as diode switches 40, 41 and 42 and function to remove the preceding largest signal as an input to the nth analog signal 0R circuit.

The signals from the

correlation amplifiers

10, 11 and 12 are simultaneously applied to the plurality of analog signal OR circuits. The diode switches associated with each analog signal OR circuit will all be forward-biased because each of the

transistors

18, 19 and 20 will be initially cutoff. However, the largest causes the diode D1 to be reverse biased whereby the output signalfrom correlation amplifier will not be applied to the base of transistor 30. However, the output signal from correlation amplifiers 11 and 12 will be applied to the bases of

transistors

31 and 32 because the associated

diode switches

41 and 42 will be forward-biased inasmuch as

transistors

19 and 20 are held -cut off by the rise in voltage at their emitters due to the on state of transistor 18. It should be noted that resistor R12 connected between the base of transistor 30 and voltage bus 22 function in combination with resistors R9 and diode clamp D20 to bias transistor 30 OFF and to provide bias current for diode D1 and D2 when they are forward-biased, i.e., when switch 40 is ON. Diode clamp D20 establishes a reference potential for the base of transistor 30.

The next largest signal can appear at either

output terminal

71 or 72, but not at 70 because the input from correlation amplifier 10 has been removed by switch 40. If it is assumed that the next largest signal is from the output of correlation amplifier 12, it will be identified at output terminal 72. Transistor 32 will be on and

transistors

30 and 31 will becutoff. With transistor 32 on, diode switch 62 will be OFF because diode D11 is reverse biased. Thus, the output from correlation amplifier 12 will not be applied to the analog signal OR circuits formed by

transistors

50, 51 and 52. Also, diode switch 60 will OFF because transistor 18 is still on. Hence, the next largest signal will appear at output terminal 81.

In order to determine the difference between one largest signal and the next largest signal, the emitter outputs from the analog signal OR circuits are compared by means of a differential amplifier. Since the

transistors

18, 19 and 20 are connected as emitter followers, the largest signal will appear on conductor 21 which is connected to one input of differential amplifier 90. The next largest signal appears on conductor 23 which is connected as the other input to differential amplifier 90. The difference in magnitudes between the signals on

conductors

21 and 23 will appear at output terminal 91. in a similar manner, differential amplifier 95 has inputs from conductor 23 and conductor 24 to compare the second largest signal with the nth largest signal. The difference in magnitude between these two signals will appear at output terminal 96. The largest, next largest and nth largest signals appear at terminals 92, 93 and 94 respectively. a

The circuitry in FIG. 2 shows the invention for two orders. The resistors R4 and R8 are replaced by current sources 100 and 101 respectively. Note that the input circuits to the

transistors

18 and 19, only transistor 18 being shown, are slightly modified in actual practice. However, the operation is as previously described.

The feedback, control diode switches can be modified as shown in H6. 3. In order to simplify the illustration, only the modification for diode switch 40 is shown. The other diode switches, 41, 42, 60, 61 and 62,

' would be modified in a similar manner. in FIG. 3, the

collector of transistor 18 is applied to logic inverter 106. The output of inverter 106 is applied to output terminal 26 and is also fed back to the base of transistor 107. The emitter of transistor 107 is connected to ground or a voltagelower than the lowest signal expected at the output of 10 and the collector is connected to a point between diodes D1 and D2. This same point is also connected to the positive potential source +V via resistor R99. According to this arrangement, when transistor 18 is ON, the inverted signal from inverter 106 turns transistor 107 ON. With transistor 107 ON, switch 40 is turned OFF because diode D1 will be reverse biased. The advantage of this arrangement is that the inverter 106 provides isolation from logic circuits, not shown, connected to output terminal 26. Inverter 106 also provides digital switch control in the feedback path.

From the foregoing, it is seen that an analog decision circuit has been provided for identifyingand ordering analog signals of a group of analog signals according to their magnitudes. The identification and ordering of these signals takes place simultaneously rather than sequentially. This enables the determination of the difference between one largest signal and the next largest signal.

What is claimed is:

1. An analog decision circuit for simultaneously identifying and ordering analog signals of a group of analog signals according to their magnitudes comprismg;

an analog signal OR circuit for each order, each analog signal OR circuit having inputs for simultaneously receiving said analog signals and outputs for identifying the largest analog signal and an output on which the largest analog signal will appear for said order, and

a switch for each analog signal input of each order of analog signal OR circuits except the highest order connected to apply the associated analog signal to the associated input when on and connected to be switched off by the identifying output of a. higher order position analog signal OR circuit having the same analog signal input when said identifying output identifies said analog signal input as being the largest analog signal.

2. The analog decision circuit of claim 1 where said analog signal OR circuits have an emitter follower transistor for each analog input.

3. The analog decision circuit of claim 2wherein the identifying outputs of each analog signal OR circuit are connected to the collectors of said emitter followers and the output for said analog circuit on which the largest analog signal for that order will appear is commonly connected to the emitters of said emitter followers of that order.

4. The analog decision circuit of claim 1 where said switches include a pair of diodes connected so that the switch is normally on.

S. The analog decision circuit of claim 3 further comprising an inverter corresponding to and connected to the collector of each transistor in each order of analog signal OR circuits and prising determining means for determining the difference in magnitude between the largest analog signal for one order and the largest analog signal for another order.

7. The analog decision circuit of claim 6 wherein said determining means is adifferential amplifier.

Claims

1. An analog decision circuit for simultaneously identifying and ordering analog signals of a group of analog signals according to their magnitudes comprising; an analog signal OR circuit for each order, each analog signal OR circuit having inputs for simultaneously receiving said analog signals and outputs for identifying the largest analog signal and an output on which the largest analog signal will appear for said order, and a switch for each analog signal input of each order of analog signal OR circuits except the highest order connected to apply the associated analog signal to the associated input when on and connected to be switched off by the identifying output of a higher order position analog signal OR circuit having the same analog signal input when said identifying output identifies said analog signal input as being the largest analog signal.

3. The analog decision circuit of claim 2 wherein the identifying outputs of each analog signal OR circuit are connected to the collectors of said emitter followers and the output for said analog circuit on which the largest analog signal for that order will appear is commonly connected to the emitters of said emitter followers of that order.

5. The analog decision circuit of claim 3 further comprising an inverter corresponding to and connected to the collector of each transistor in each order of analog signal OR circuits and a transistor driver corresponding to and connected to each inverter in each order to be turned on when there is an output on the corresponding collector, the output of said transistor driver being connected to corresponding switches of lower orders to turn the same off.

6. The analog decision circuit of claim 1 further comprising determining means for determining the difference in magnitude between the largest analog signal for one order and the largest analog signal for another order.