GB1281387A - Associative store - Google Patents

Associative store

Info

Publication number
GB1281387A
GB1281387A GB5724169A GB5724169A GB1281387A GB 1281387 A GB1281387 A GB 1281387A GB 5724169 A GB5724169 A GB 5724169A GB 5724169 A GB5724169 A GB 5724169A GB 1281387 A GB1281387 A GB 1281387A
Authority
GB
United Kingdom
Prior art keywords
cells
interrogation
state
cell
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5724169A
Inventor
Peter Lycett Gardner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to GB5724169A priority Critical patent/GB1281387A/en
Priority to FR7036307A priority patent/FR2068589B1/fr
Priority to CA097532A priority patent/CA935885A/en
Priority to DE19702057124 priority patent/DE2057124A1/en
Publication of GB1281387A publication Critical patent/GB1281387A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5057—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using table look-up; using programmable logic arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4804—Associative memory or processor

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Optimization (AREA)
  • Electronic Switches (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

1281387 Transistor bi-stable circuits INTERNATIONAL BUSINESS MACHINES CORP 22 Nov 1969 57241/69 Heading H3T [Also in Division G4] An associative store comprises an array of two state (1, X) cells, one of the sates (the X state) being such that a mismatch signal is not generated when the cell is interrogated, irrespective of whether the interrogation is for binary " 1 " or binary " 0 ". In an embodiment, Fig. 2 (not shown), the cells consist of a single emitter junction transistor cross-coupled with a double emitter junction transistor. In the " X " state with the single emitter transistor conductive no current is passed to the sense line during an interrogation. In a second embodiment, Fig. 9 (not shown), the cells consist of two cross-coupled double emitter transistors. These cells have two modes of operation. In the first the cell functions as described above. In the second the cell functions as a normal 1, 0 associative cell with mismatch signals being developed in both states under the appropriate interrogation. The mode of the cells is determined by a bistabletrigger connected to each column of the store.
GB5724169A 1969-11-22 1969-11-22 Associative store Expired GB1281387A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB5724169A GB1281387A (en) 1969-11-22 1969-11-22 Associative store
FR7036307A FR2068589B1 (en) 1969-11-22 1970-09-28
CA097532A CA935885A (en) 1969-11-22 1970-11-06 Two-state associative arrays
DE19702057124 DE2057124A1 (en) 1969-11-22 1970-11-20 Associative memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB5724169A GB1281387A (en) 1969-11-22 1969-11-22 Associative store

Publications (1)

Publication Number Publication Date
GB1281387A true GB1281387A (en) 1972-07-12

Family

ID=10478713

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5724169A Expired GB1281387A (en) 1969-11-22 1969-11-22 Associative store

Country Status (4)

Country Link
CA (1) CA935885A (en)
DE (1) DE2057124A1 (en)
FR (1) FR2068589B1 (en)
GB (1) GB1281387A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2176920A (en) * 1985-06-13 1987-01-07 Intel Corp Content addressable memory
US5321836A (en) * 1985-06-13 1994-06-14 Intel Corporation Virtual memory management method and apparatus utilizing separate and independent segmentation and paging mechanism
US6842360B1 (en) 2003-05-30 2005-01-11 Netlogic Microsystems, Inc. High-density content addressable memory cell
US6856527B1 (en) 2003-05-30 2005-02-15 Netlogic Microsystems, Inc. Multi-compare content addressable memory cell
US7174419B1 (en) 2003-05-30 2007-02-06 Netlogic Microsystems, Inc Content addressable memory device with source-selecting data translator

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2454427C2 (en) * 1974-11-16 1982-04-29 Ibm Deutschland Gmbh, 7000 Stuttgart Associative memory

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1128576A (en) * 1967-07-29 1968-09-25 Ibm Data store
GB1186703A (en) * 1967-10-05 1970-04-02 Ibm Associative Memory

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2176920A (en) * 1985-06-13 1987-01-07 Intel Corp Content addressable memory
GB2176920B (en) * 1985-06-13 1989-11-22 Intel Corp Content addressable memory
US5321836A (en) * 1985-06-13 1994-06-14 Intel Corporation Virtual memory management method and apparatus utilizing separate and independent segmentation and paging mechanism
US6842360B1 (en) 2003-05-30 2005-01-11 Netlogic Microsystems, Inc. High-density content addressable memory cell
US6856527B1 (en) 2003-05-30 2005-02-15 Netlogic Microsystems, Inc. Multi-compare content addressable memory cell
US6901000B1 (en) 2003-05-30 2005-05-31 Netlogic Microsystems Inc Content addressable memory with multi-ported compare and word length selection
US7174419B1 (en) 2003-05-30 2007-02-06 Netlogic Microsystems, Inc Content addressable memory device with source-selecting data translator

Also Published As

Publication number Publication date
CA935885A (en) 1973-10-23
FR2068589A1 (en) 1971-08-27
FR2068589B1 (en) 1974-05-24
DE2057124A1 (en) 1971-06-03

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee