JPS5926056B2 - Current mode carry hold adder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to digital electronic circuits, and more particularly to current mode logic circuits that provide carry-and-hold adders.

Carry-and-hold adders are a known technique.

It operates on three inputs A, B, ClN and two outputs S and C. OT is generated by applying the following logical formula.
A carry-and-hold adder is an extremely useful basic logic element for combining with other components to form the basic processing element of a digital information processing device.

Examples and explanations of such use can be found in Ivan Floors (Iv
anFlOres), Prentice Hall (Pren
The Logic of Computer Arithmetic (The LOgic of Carlpu-Ter.
Arithnletic]. Current mode logic (CML) is a relatively new form of microcircuitry that has a pair of transistors combined to form a gate that has a continuous current flowing through them; flowing through one of the two transistors of each pair. CML circuits are extremely fast and low power. It is therefore an object of the present invention to provide a carry-and-hold adder that uses current mode logic.

Another object of the invention is to provide an improved carry-and-hold adder for use with arithmetic logic elements in digital computing machines. Still another object of the invention is to provide an improved carry-and-hold adder for use with arithmetic logic elements in digital computing machines. The purpose of the present invention is to provide a carry-hold adder.

Other objects and features of the invention will become apparent from the following description.

The present invention includes circuitry that provides a carry-hold-add function.

The circuit is responsive to three binary inputs corresponding to add bit A, addend bit B, and one carry bit ClN, sum bit S and carry bit C. It produces two output signals corresponding to OT. Both the input and output signals vary from ground potential (logic 0) to -0.5 volts (logic 1). This circuit is implemented using current mode logic, with two half adders combined to provide a carry-and-hold adder. Due to the need for minimum operating time, size, and power consumption, the gates in this circuit are connected in series. Each half-adder has only one current source, which supplies current to all gates within that unit. Each half adder operates on two input signals and provides a partial sum signal and a partial sum carry signal. Each half adder is
It consists of upper and lower gates that operate as current switches with different reference voltages. Referring to the drawings, FIG. 1 is a block diagram of the present invention.

Block 100 is a half adder. The input signal A (5B) is calculated and the partial sum carrier (A-B
), but an output signal corresponding to the partial sum of A and B (sweat pressure) is output on the conductor 135. The basic elements of half-adder 100 are blocks 105, 110, 115, 120 and 125, which are functionally described in the discussion with respect to FIGS. 2-4. Block 1
05 and 110 are the upper gates. The Y input of each gate is the A signal. The other inputs Z of these gates are the actual output signal from block 120 and its complementary output signal. The block 120 receives an input signal from an emitter follower 125 at a lower buffer gate and generates an actual output signal and its supplementary output signal. Since emitter follower 125 is responsive to the B signal, the real and complementary output signals from block 120 correspond to B and B, respectively. Therefore, the B signal is sent to gate 105 and the B signal is sent to gate 110. Returning to blocks 105 and 110, the YZ output signal of block 105 and the YZ output signal of block 110 are combined by OR gate 115.

Therefore, input signals AB and AB are connected to AB on conductor 135.
+AB signal, which output signal is the exclusive OR of the A and B signals, which also corresponds to the partial sum of A and B. Y of block 105
The Z output signal is output on conductor 130, which corresponds to AB and is equal to the partial sum of A and B. Block 100 is therefore equivalent to a half adder. Block 2
00 is a half adder similar to block 100. However, the block 200 receives the input signal from conductor 135, the partial sum of A(5B), and the input signal ClN.
acts on The output signal of this block is
5 and the partial sum carry signal (for its two inputs) on conductor 230. The two partial sum carry signals are sent to OR gate 300.

OR gate 300 combines these signals to produce a carry-to-carry signal C for the carry-to-hold adder. Generate OT. Next, a current mode implementation of the basic program of the carry-and-hold adder according to the invention will be described.

The most important blocks are shown in FIGS. 2-4. In the drawings, logic diagrams or symbols are illustrated along with schematic diagrams of equivalent electronic circuits. As described, the series gate included in the lower gate and the upper gate is such that its output voltage swing is approximately 0.5 volts. This voltage amplitude limitation reduces power requirements and transition times. Figure 2A shows input A and output B.
It is the symbol of Emituta Followa.

Emitter followers are typically used where the A signal has a large fanout (i.e. where it feeds multiple input circuits).
used in circuits. An equivalent electronic circuit is shown in FIG. 2B, where input A is fed to the base of transistor 28 and output B is taken from the common terminal of transistor 28's emitter and resistor 29. FIG. 3A is a lower buffer gate with an input A, an actual output C (logically equal to A), and an auxiliary output B (logically equal to A). In the electronic scheme of FIG. 3B, input A is provided to the base of transistor 34, a (lower) reference voltage of approximately -1.06 volts is provided to the base of transistor 35, and the common voltage of transistors 34 and 35 is The emitter is connected to a current source 36. Output B is transistor 3
The output C is taken out from the collector of transistor 3.
5 collector. The upper gate of FIG. 4A has C and D output terminals respectively supplied with inputs A.l!1.B at terminals Y(5Z) and outputting YZ and YZ outputs, respectively.

In the equivalent electronic diagram, FIG. AB, input A is applied to the base of transistor 41 and input B is applied to the common emitter terminal of transistors 41 and 42. -0
．． A (top) reference voltage of 26 volts is provided to the base of transistor 42, and the collectors of transistors 41 and 42 are connected to ground through resistors 43 and 44, respectively. The C output is taken out from the collector of transistor 41, and the D output is taken out from the collector of transistor 42. With the basic functional elements defined by the above logic diagram and equivalent circuit, we will now turn to a detailed explanation of the carry-and-hold adder shown in FIG. The circuit will be explained.

Note, however, that the upper gate shown in FIG. 5 is slightly different from FIG. These differences are shown in FIG.
Due to the restriction of inclusion of resistance, as shown as part of . The inclusion of these resistors as part of the first type of subunit as opposed to the second type is optional and, as can be readily appreciated by those skilled in the art,
This is not essential to an understanding of the invention.

Referring to FIG. 5, a detailed circuit diagram of the present invention is shown. The reference numbers in FIGS. 1 and 5 indicate the same subunits in both figures. Inputs A and B are stabilizer circuit 1
50 to the half adder 100. Stability circuit 1
50 serves no logical function. Input B is stabilizer circuit 150
is connected to the emitter follower 125 by. The output signal from emitter follower 125 is connected to Q4 of portion 121 of lower buffer gate 120. Part 121
The base of Q6 is connected to a lower reference voltage source 160.
The collector of Q6 follows signal B, whereas the collector of Q4 is inverted with respect to B. The inverted signal is connected to the Z terminal of gate 110, and the real signal is connected to gate 0.
Connected to the Z input of 5. Buffer gate 120 includes a portion 121 consisting of transistor pair Q4 and Q6.
The buffer gate 120 has a portion 1 which is an effective constant current source.
Also includes 22. Constant current source 122 is driven by constant voltage source 400. The lower reference voltage source 160 is a reference voltage VR of −0.26 volts, which is a voltage signal supplied from the outside.
Includes an emitter follower driven by EF. Output signal AB from YZ terminal of gate 10 and gate 105
The output signal AB from the YZ terminal of is combined by an OR gate 115 to form an exclusive OR signal of A and B on a conductor 135. Conductor 130 provides a partial sum carry signal to OR gate 300. Half adder 200 operates in a similar manner on the signal from conductor 135 and the ClN signal.

The ClN signal is provided to emitter follower 225 by ballast circuit 250. Emitter follower 225 provides an input signal to buffer gate 220 . A lower reference voltage signal is provided to gate 220 by reference voltage unit 260. Reference voltage unit 260 is another emitter follower driven by the upper reference voltage signal VRE. Buffer gate 220 consists of two parts, part 221 consists of transistor pair Ql4,Q
The portion 222 in l6 is a constant current source. Portions 222 are driven by a common constant voltage source 400. gate 205
and 210 receive input signals, calculate the exclusive OR of these inputs, and output the result through OR gate 215. The output of OR gate 300 is the sum of C. This is an OT signal. The other output of half adder 200 is fed to conductor 235 which is connected to the three input signals A, B and C.
Corresponds to the sum signal of IN. The input and output logic signals vary from ground level to -0.5 volts.

Therefore, negative logic is utilized, with the ground level signal corresponding to a logic 0 and the -0.5 volt signal power corresponding to a logic 1. In the series connection design of the present invention, the upper gate is from O to −0.5
The lower gate is driven by a volt signal whereas the lower gate is driven by -0.8 to -1.3 volts, the difference being due to the 0.8 volt base-emitter voltage drop. be equivalent to. Therefore −0 supplied to the upper gate
．． A reference voltage equal to 26 volts must be converted to provide a lower reference voltage. This is half adder 1
These provide a lower reference voltage of -1.06 volts for 00 and 200, respectively, provided by units 160 and 260. All transistors shown are bibolar transistors.

Desired capacitances of capacitors C1 and C25 are both 2PF.
It is. Desired resistance values for the unique features of the present invention are shown in the following table. The advantage of the serial gate CML implementation of the carry-and-hold adder is the reduction in power, space and time.

Because of the series-connected design, only one current source is required for each half-adder. Therefore, in the present invention, power consumption is lower and the amount of heat generated by the element is also lower. Similarly, the need for only one current source per half-adder is an advance over the traditional need for one current source per gate. The carry-hold adder according to the prior art is
It contained five gates, each with an attached current source.

Eliminating unnecessary current sources clearly results in a reduction in space. The series gate design also reduced special space requirements. Finally, series gating resulted in less gate delay. The prior art required essentially three gate delays to produce the partial sum. In embodiments of the invention, substantially 1
There is only a gate delay of ± from . Since the carry-and-hold adder is an essential component of many parts within modern information processing equipment, a reduction in time of more than 50% in its operation will substantially reduce the overall time and the present invention Reduces the overall time required for information processing equipment using Although the invention has been described with reference to particular embodiments, this description is illustrative and should not be construed as limiting the scope of the invention.

It will be obvious to those skilled in the art that various changes and modifications can be made without departing from the true spirit of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a carry-and-hold adder according to the present invention.

Claims (1)

Claims: 1. A half-adder comprising a current mode logic circuit and receiving first and second input signals, each representing a binary number, comprising one signal input lead, one current input lead, a first and a second current output conductor, and when a binary signal Y is input to the signal input conductor and a binary signal Z is input to the current input conductor, a second current output conductor is output from the first current output conductor.
The binary logic signal @Y@Z is outputted from the second current output conductor by the binary logic signal YZ, the first and second upper gates, the first and second input terminals, and one output terminal. wherein the first input terminal is coupled to a second current output conductor of the first upper gate, and the second input terminal is coupled to the first current output conductor of the second upper gate. a logic OR gate and a lower gate having one signal input conductor and first and second current output conductors, wherein when a binary signal is input to the signal input conductor of the lower gate; said lower gate, wherein said binary signal is conveyed by a first current output conductor of said lower gate, and said binary signal is conveyed by said second current output conductor of said lower gate; the first current output conductor coupled to the first upper gate current input conductor and the lower gate second current output conductor coupled to the second upper gate current input conductor; a device for connecting each of the first and second upper gates in series to the lower gate; and connecting the first input signal of the half adder to a signal input lead of each of the upper gates; a device for connecting the second input signal of the half adder to the signal input conductor of the lower gate, the output signal of the output terminal of the logic OR gate being connected to the second input signal of the half adder; 1 and a second input signal, and the signal carried by the first current output conductor of the first upper gate represents the binary exclusive OR of the first and second input signals of the half adder. 2
Said half adder, characterized in that it represents an advance product. 2. A full adder for responding to three input signals and supplying a first output signal corresponding to the sum of the input signals and a second output signal corresponding to the carry of the sum of the input signals, , an upper gate responsive to a first input signal and a first reference voltage signal, and a lower gate responsive to a second input signal, a lower input signal, and a second reference voltage signal; a first partial sum in response to the first and second of the input signals, the upper and lower gates being connected in series such that the side gate supplies current to the upper gate; for providing a carry signal for the signal and the first partial sum signal;
a first half adder; an upper gate responsive to the first partial sum signal and the first reference voltage signal; It consists of a responsive lower gate, the upper and lower gates connected in series such that the lower gate supplies current to the upper gate. a second partial sum signal corresponding to the first output signal in response to the third input signal and the first partial sum signal;
a second half adder for providing a carry signal of the partial sum signal of the first and second partial sum signals; and a second half adder for providing the second output signal in response to the carry signal of the first and second partial sum signals. 1 gate device. 3. The full adder according to claim 2, wherein the first gate device includes a hardwired OR circuit. Said full adder. 4. The full adder according to claim 2, wherein the lower gate includes a device for supplying a constant current and, in response to the constant current device, real and supplementary output signals related to the lower input signal. a first device for supplying the upper gate to the upper gate. 5. The full adder according to claim 2, wherein each of the first and second upper gates includes one signal input conductor, one current input conductor, and first and second current output conductors. When a binary signal Y is input to the signal input conductor and a binary signal Z is input to the current input conductor, a binary AND signal YZ is output from the first current output conductor to the Binary AND signal @Y@Z from the second current output conductor
is output, and the lower gate includes one signal input conductor and first and second current output conductors, and a binary signal is input to the signal input conductor of the lower gate. when the binary signal is transmitted by the first current output conductor of the lower gate, and the complement signal of the binary signal is transmitted by the second current output conductor of the lower gate. and each of the first and second half adders is provided with a logical OR gate having first and second input terminals and one output terminal;
an input terminal of the first upper gate is coupled to a second current output conductor of the first upper gate; the second input terminal is coupled to a first current output conductor of the second upper gate; Each of the first and second half-adders couples the first current output conductor of the lower gate to the current input conductor of the first upper gate; an apparatus for connecting the lower gate in series with each of the first and second upper gates by coupling a current output conductor to a current input conductor of the second upper gate; an apparatus for connecting an input signal to a signal input lead of the first and second upper gates, and a device for connecting the second input signal to a signal input lead of the lower gate; The output terminal of the OR gate outputs the binary exclusive OR of the binary signals Y and Z of the first and second half adders, and the output terminal of the logical OR gate of the first half adder is the third input signal is connected to a signal input lead of each of the first and second upper gates of the second half adder, and the third input signal is connected to a signal input lead of the lower gate of the second half adder. 2 of the first, second, and third input signals of the first half adder and the third input signal of the full adder from the output terminal of the logic OR gate of the second half adder.
It is characterized in that a sum signal is output. Said full adder. 6. The full adder according to claim 5, comprising: the first gate device; a logical OR gate having first and second input terminals; and one output terminal; an input terminal of is coupled to a first current output conductor of a first upper gate of the first half-adder;
The second input terminal is coupled to a first current output conductor of the first upper gate of the second half-adder, and the signal carried by the output terminal of the logic OR gate of the first gating device is , the signal representing a binary sum carry of the first and second input signals of the first half adder and the third input signal.