DE2619418C2 - Einrichtung zum Umsetzen einer Binärzahl in eine Zahl Modulo M - Google Patents

Einrichtung zum Umsetzen einer Binärzahl in eine Zahl Modulo M

Info

Publication number
DE2619418C2
DE2619418C2 DE2619418A DE2619418A DE2619418C2 DE 2619418 C2 DE2619418 C2 DE 2619418C2 DE 2619418 A DE2619418 A DE 2619418A DE 2619418 A DE2619418 A DE 2619418A DE 2619418 C2 DE2619418 C2 DE 2619418C2
Authority
DE
Germany
Prior art keywords
adder
binary
modulo
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2619418A
Other languages
German (de)
English (en)
Other versions
DE2619418A1 (de
Inventor
Chandrakant Ratilal Audubon Pa. Vora
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of DE2619418A1 publication Critical patent/DE2619418A1/de
Application granted granted Critical
Publication of DE2619418C2 publication Critical patent/DE2619418C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • H03M7/18—Conversion to or from residue codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE2619418A 1975-05-09 1976-05-03 Einrichtung zum Umsetzen einer Binärzahl in eine Zahl Modulo M Expired DE2619418C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/576,002 US3980874A (en) 1975-05-09 1975-05-09 Binary to modulo M translation

Publications (2)

Publication Number Publication Date
DE2619418A1 DE2619418A1 (de) 1976-11-18
DE2619418C2 true DE2619418C2 (de) 1986-05-15

Family

ID=24302582

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2619418A Expired DE2619418C2 (de) 1975-05-09 1976-05-03 Einrichtung zum Umsetzen einer Binärzahl in eine Zahl Modulo M

Country Status (9)

Country Link
US (1) US3980874A (https=)
JP (1) JPS5932817B2 (https=)
BE (1) BE838859A (https=)
BR (1) BR7602549A (https=)
CA (1) CA1075818A (https=)
DE (1) DE2619418C2 (https=)
FR (1) FR2310592A1 (https=)
GB (3) GB1513229A (https=)
NL (1) NL7603875A (https=)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051551A (en) * 1976-05-03 1977-09-27 Burroughs Corporation Multidimensional parallel access computer memory system
US4041284A (en) * 1976-09-07 1977-08-09 The United States Of America As Represented By The Secretary Of The Navy Signal processing devices using residue class arithmetic
US4095275A (en) * 1977-02-14 1978-06-13 Westinghouse Electric Corp. Pulse width modulated sine cosine generator
US4190893A (en) * 1977-11-17 1980-02-26 Burroughs Corporation Modular modulo 3 module
US4202035A (en) * 1977-11-25 1980-05-06 Mcdonnell Douglas Corporation Modulo addressing apparatus for use in a microprocessor
FR2420167B1 (fr) * 1978-03-14 1985-10-04 Constr Telephoniques Systeme de manipulation de champs d'elements binaires
US4189767A (en) * 1978-06-05 1980-02-19 Bell Telephone Laboratories, Incorporated Accessing arrangement for interleaved modular memories
US4187549A (en) * 1978-09-05 1980-02-05 The United States Of America As Represented By The Secretary Of The Navy Double precision residue combiners/coders
US4218587A (en) * 1978-09-18 1980-08-19 Storage Technology Corporation Complex signal generation and transmission
US4433389A (en) * 1978-12-26 1984-02-21 Burroughs Corporation Memory address translation system for accessing memory locations via job names
US4281391A (en) * 1979-01-15 1981-07-28 Leland Stanford Junior University Number theoretic processor
JPS55161281A (en) * 1979-06-01 1980-12-15 Canon Kk Display control unit
US4418394A (en) * 1980-08-13 1983-11-29 Environmental Research Institute Of Michigan Optical residue arithmetic computer having programmable computation module
JPS5936854A (ja) * 1982-08-25 1984-02-29 Matsushita Electric Ind Co Ltd 自然数の剰余数変換装置
US4538238A (en) * 1983-01-18 1985-08-27 Honeywell Information Systems Inc. Method and apparatus for calculating the residue of a signed binary number
US4555769A (en) * 1983-05-25 1985-11-26 International Business Machines Corporation Circuit apparatus for generating modulus-N residues
DE3326044A1 (de) * 1983-07-20 1985-02-07 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zur ausfuehrung der galois-feld-multiplikation oder -division und schaltungsanordnung zur durchfuehrung des verfahrens
JPH0681164B2 (ja) * 1984-02-01 1994-10-12 株式会社日立製作所 符号変調方式
US4722067A (en) * 1985-03-25 1988-01-26 Motorola, Inc. Method and apparatus for implementing modulo arithmetic calculations
US4742479A (en) * 1985-03-25 1988-05-03 Motorola, Inc. Modulo arithmetic unit having arbitrary offset and modulo values
JPS6270936A (ja) * 1985-09-24 1987-04-01 Nec Corp モジユロ３剰余発生器
JPS63200233A (ja) * 1987-02-16 1988-08-18 Fujitsu Ltd 高速並列乗除計算機
JP2553548B2 (ja) * 1987-03-27 1996-11-13 松下電器産業株式会社 乗算剰余演算装置
US4833602A (en) * 1987-06-29 1989-05-23 International Business Machines Corporation Signal generator using modulo means
EP0308963A3 (en) * 1987-09-25 1990-04-25 Kabushiki Kaisha Toshiba Remainder computing system and method
KR0129751B1 (ko) * 1987-10-12 1998-10-01 오가 노리오 잉여수시스템에 있어서의 데이타의 엔코딩장치 및 디코딩장치와 방법
US5293607A (en) * 1991-04-03 1994-03-08 Hewlett-Packard Company Flexible N-way memory interleaving
US5617538A (en) * 1991-07-02 1997-04-01 Tm Patents, L.P. Message transfer system and method for parallel computer with message transfers being scheduled by skew and roll functions to avoid bottlenecks
JPH0720778A (ja) * 1993-07-02 1995-01-24 Fujitsu Ltd 剰余計算装置、テーブル作成装置および乗算剰余計算装置
KR950015177B1 (ko) * 1993-12-06 1995-12-23 한국전기통신공사 사전 계산 테이블을 이용한 모듈로 리덕션 방법
US5623423A (en) * 1994-12-12 1997-04-22 Univ. Of Texas Apparatus and method for video decoding
US8229109B2 (en) * 2006-06-27 2012-07-24 Intel Corporation Modular reduction using folding
US7827471B2 (en) * 2006-10-12 2010-11-02 Intel Corporation Determining message residue using a set of polynomials
US8689078B2 (en) 2007-07-13 2014-04-01 Intel Corporation Determining a message residue
US7886214B2 (en) * 2007-12-18 2011-02-08 Intel Corporation Determining a message residue
US8042025B2 (en) * 2007-12-18 2011-10-18 Intel Corporation Determining a message residue
US8886898B2 (en) * 2009-08-19 2014-11-11 Oracle America, Inc. Efficient interleaving between a non-power-of-two number of entities
US8930431B2 (en) * 2010-12-15 2015-01-06 International Business Machines Corporation Parallel computation of a remainder by division of a sequence of bytes
US8984039B2 (en) 2012-02-06 2015-03-17 International Business Machines Corporation Residue-based error detection for a processor execution unit that supports vector operations

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3137788A (en) * 1960-11-04 1964-06-16 Emi Ltd Error checking system using residue redundancy
US3316393A (en) * 1965-03-25 1967-04-25 Honeywell Inc Conditional sum and/or carry adder
US3863248A (en) * 1973-01-02 1975-01-28 Univ Sherbrooke Digital compressor-expander
US3882483A (en) * 1973-05-07 1975-05-06 Electronic Associates Code converter system and method

Also Published As

Publication number Publication date
GB1513103A (en) 1978-06-07
DE2619418A1 (de) 1976-11-18
US3980874A (en) 1976-09-14
BR7602549A (pt) 1976-11-16
FR2310592A1 (fr) 1976-12-03
NL7603875A (nl) 1976-11-11
GB1513229A (en) 1978-06-07
GB1513102A (en) 1978-06-07
JPS5932817B2 (ja) 1984-08-11
CA1075818A (en) 1980-04-15
BE838859A (fr) 1976-06-16
JPS5284937A (en) 1977-07-14
FR2310592B1 (https=) 1980-10-31

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8128 New person/name/address of the agent

Representative=s name: EISENFUEHR, G., DIPL.-ING. SPEISER, D., DIPL.-ING.

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee