DE2456742A1 - Verfahren zur erzeugung des n-fachen einer normalfrequenz - Google Patents

Verfahren zur erzeugung des n-fachen einer normalfrequenz

Info

Publication number
DE2456742A1
DE2456742A1 DE19742456742 DE2456742A DE2456742A1 DE 2456742 A1 DE2456742 A1 DE 2456742A1 DE 19742456742 DE19742456742 DE 19742456742 DE 2456742 A DE2456742 A DE 2456742A DE 2456742 A1 DE2456742 A1 DE 2456742A1
Authority
DE
Germany
Prior art keywords
frequency
pulse
counter
phase
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19742456742
Other languages
German (de)
English (en)
Inventor
Rolf Witschi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hasler AG
Original Assignee
Hasler AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hasler AG filed Critical Hasler AG
Publication of DE2456742A1 publication Critical patent/DE2456742A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/18—Temporarily disabling, deactivating or stopping the frequency counter or divider

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE19742456742 1973-12-20 1974-11-30 Verfahren zur erzeugung des n-fachen einer normalfrequenz Pending DE2456742A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1788973A CH566089A5 (no) 1973-12-20 1973-12-20

Publications (1)

Publication Number Publication Date
DE2456742A1 true DE2456742A1 (de) 1975-06-26

Family

ID=4428858

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19742456742 Pending DE2456742A1 (de) 1973-12-20 1974-11-30 Verfahren zur erzeugung des n-fachen einer normalfrequenz

Country Status (7)

Country Link
JP (1) JPS50115458A (no)
CH (1) CH566089A5 (no)
DE (1) DE2456742A1 (no)
GB (1) GB1452559A (no)
IT (1) IT1032558B (no)
NL (1) NL7416281A (no)
SE (1) SE398423B (no)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2502435A1 (fr) * 1981-03-20 1982-09-24 Victor Company Of Japan Dispositif multiplicateur de la frequence de balayage horizontal
EP0089372A1 (en) * 1981-09-28 1983-09-28 Honeywell Inc. System for preventing transient induced errors in phase locked loop
FR2526619A1 (fr) * 1982-05-06 1983-11-10 Victor Company Of Japan Circuit de multiplication de la frequence de balayage
EP0645892A1 (fr) * 1993-09-28 1995-03-29 France Telecom Dispositif d'asservissement de fréquence
WO1995018508A1 (en) * 1993-12-29 1995-07-06 Zenith Electronics Corporation Circuit for the acquisition of a carrier signal by applying a substitute pilot to a synchronous demodulator
WO1997023049A1 (en) * 1995-12-20 1997-06-26 Italtel S.P.A. Procedure and circuit for holding lock state in a digital pll

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE7411960L (sv) * 1974-09-24 1976-03-25 Fabriker As Haustrups Sett att framstella behallare sasom flaskor eller burkar av polyester
US4290028A (en) * 1979-07-30 1981-09-15 International Telephone And Telegraph Corporation High speed phase locked loop frequency synthesizer
JPS5720052A (en) 1980-07-11 1982-02-02 Toshiba Corp Input data synchronizing circuit
GB2132042B (en) * 1982-12-15 1986-09-24 British Broadcasting Corp Frequency and timing sources
WO1999013582A1 (en) * 1997-09-09 1999-03-18 Advanced Fibre Communications, Inc. Perturbation tolerant digital phase-locked loop employing phase-frequency detector
EP2158677B1 (en) 2007-06-14 2018-05-30 NXP USA, Inc. Circuit arrangement for filtering unwanted signals from a clock signal, processing system and method of filtering unwanted signals from a clock signal
WO2010076667A1 (en) 2009-01-05 2010-07-08 Freescale Semiconductor, Inc. Clock glitch detection circuit
WO2010112969A1 (en) 2009-03-31 2010-10-07 Freescale Semiconductor, Inc. Clock glitch detection

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2502435A1 (fr) * 1981-03-20 1982-09-24 Victor Company Of Japan Dispositif multiplicateur de la frequence de balayage horizontal
EP0089372A1 (en) * 1981-09-28 1983-09-28 Honeywell Inc. System for preventing transient induced errors in phase locked loop
EP0089372A4 (en) * 1981-09-28 1985-07-01 Honeywell Inc SYSTEM FOR ELIMINATING TRANSIENT ERRORS INDUCED IN A PHASE-LOCKED LOOP.
FR2526619A1 (fr) * 1982-05-06 1983-11-10 Victor Company Of Japan Circuit de multiplication de la frequence de balayage
EP0645892A1 (fr) * 1993-09-28 1995-03-29 France Telecom Dispositif d'asservissement de fréquence
FR2710806A1 (fr) * 1993-09-28 1995-04-07 France Telecom Dispositif d'asservissement de fréquence.
WO1995018508A1 (en) * 1993-12-29 1995-07-06 Zenith Electronics Corporation Circuit for the acquisition of a carrier signal by applying a substitute pilot to a synchronous demodulator
WO1997023049A1 (en) * 1995-12-20 1997-06-26 Italtel S.P.A. Procedure and circuit for holding lock state in a digital pll

Also Published As

Publication number Publication date
SE398423B (sv) 1977-12-19
GB1452559A (en) 1976-10-13
JPS50115458A (no) 1975-09-10
CH566089A5 (no) 1975-08-29
NL7416281A (nl) 1975-06-24
SE7415990L (no) 1975-06-23
IT1032558B (it) 1979-06-20

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