DE2432099C3 - - Google Patents

Info

Publication number
DE2432099C3
DE2432099C3 DE2432099A DE2432099A DE2432099C3 DE 2432099 C3 DE2432099 C3 DE 2432099C3 DE 2432099 A DE2432099 A DE 2432099A DE 2432099 A DE2432099 A DE 2432099A DE 2432099 C3 DE2432099 C3 DE 2432099C3
Authority
DE
Germany
Prior art keywords
transistor
transistors
zone
memory
matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2432099A
Other languages
German (de)
English (en)
Other versions
DE2432099B2 (de
DE2432099A1 (de
Inventor
Ferdinand Camerik
Cornelis Maria Hart
Arie Slob
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from NL7309453A external-priority patent/NL7309453A/xx
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE2432099A1 publication Critical patent/DE2432099A1/de
Publication of DE2432099B2 publication Critical patent/DE2432099B2/de
Application granted granted Critical
Publication of DE2432099C3 publication Critical patent/DE2432099C3/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/091—Integrated injection logic or merged transistor logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/289—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable of the primary-secondary type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/10—SRAM devices comprising bipolar components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE2432099A 1973-07-06 1974-07-04 Speichermatrix Granted DE2432099B2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL7309453A NL7309453A (nl) 1973-07-06 1973-07-06 Geheugenmatrix.
NL7408502A NL7408502A (nl) 1973-07-06 1974-06-25 Geheugenmatrix.

Publications (3)

Publication Number Publication Date
DE2432099A1 DE2432099A1 (de) 1975-02-20
DE2432099B2 DE2432099B2 (de) 1978-05-24
DE2432099C3 true DE2432099C3 (Direct) 1979-02-08

Family

ID=26644895

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2432099A Granted DE2432099B2 (de) 1973-07-06 1974-07-04 Speichermatrix

Country Status (9)

Country Link
JP (1) JPS5516354B2 (Direct)
AT (1) AT344424B (Direct)
CH (1) CH585948A5 (Direct)
DE (1) DE2432099B2 (Direct)
FR (1) FR2236248B1 (Direct)
GB (1) GB1480138A (Direct)
IT (1) IT1014450B (Direct)
NL (1) NL7408502A (Direct)
SE (1) SE399605B (Direct)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4112511A (en) * 1977-09-13 1978-09-05 Signetics Corporation Four transistor static bipolar memory cell using merged transistors
US4366554A (en) * 1978-10-03 1982-12-28 Tokyo Shibaura Denki Kabushiki Kaisha I2 L Memory device
EP0065999B1 (de) * 1981-05-30 1986-05-07 Ibm Deutschland Gmbh Hochintegrierter schneller Speicher mit bipolaren Transistoren
EP0166043B1 (en) * 1984-06-25 1990-09-19 International Business Machines Corporation Mtl storage cell with inherent output multiplex capability

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3643235A (en) * 1968-12-30 1972-02-15 Ibm Monolithic semiconductor memory

Also Published As

Publication number Publication date
DE2432099B2 (de) 1978-05-24
NL7408502A (nl) 1975-12-30
CH585948A5 (Direct) 1977-03-15
JPS5516354B2 (Direct) 1980-05-01
FR2236248B1 (Direct) 1977-10-07
DE2432099A1 (de) 1975-02-20
SE399605B (sv) 1978-02-20
JPS5050832A (Direct) 1975-05-07
GB1480138A (en) 1977-07-20
ATA558374A (de) 1977-11-15
AT344424B (de) 1978-07-25
IT1014450B (it) 1977-04-20
FR2236248A1 (Direct) 1975-01-31
SE7408741L (Direct) 1975-01-07

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee