DE2430784B2 - Bipolarer halbleiterspeicher - Google Patents
Bipolarer halbleiterspeicherInfo
- Publication number
- DE2430784B2 DE2430784B2 DE19742430784 DE2430784A DE2430784B2 DE 2430784 B2 DE2430784 B2 DE 2430784B2 DE 19742430784 DE19742430784 DE 19742430784 DE 2430784 A DE2430784 A DE 2430784A DE 2430784 B2 DE2430784 B2 DE 2430784B2
- Authority
- DE
- Germany
- Prior art keywords
- emitter
- memory
- circuit
- emitter follower
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title description 4
- 238000003860 storage Methods 0.000 title description 2
- 239000011159 matrix material Substances 0.000 claims description 9
- 230000015654 memory Effects 0.000 description 38
- 230000010354 integration Effects 0.000 description 9
- 238000011156 evaluation Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000006399 behavior Effects 0.000 description 3
- 210000004027 cell Anatomy 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000036316 preload Effects 0.000 description 2
- 241000845077 Iare Species 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009415 formwork Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/416—Read-write [R-W] circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19742430784 DE2430784B2 (de) | 1974-06-26 | 1974-06-26 | Bipolarer halbleiterspeicher |
| US05/583,690 US4005393A (en) | 1974-06-26 | 1975-06-04 | Bipolar semiconductor memory with recharging circuit for capacitively loaded lines |
| FR7519915A FR2276655A1 (fr) | 1974-06-26 | 1975-06-25 | Memoire a semiconducteurs bipolaire |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19742430784 DE2430784B2 (de) | 1974-06-26 | 1974-06-26 | Bipolarer halbleiterspeicher |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE2430784A1 DE2430784A1 (de) | 1976-01-15 |
| DE2430784B2 true DE2430784B2 (de) | 1977-02-10 |
Family
ID=5919049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19742430784 Granted DE2430784B2 (de) | 1974-06-26 | 1974-06-26 | Bipolarer halbleiterspeicher |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4005393A (enExample) |
| DE (1) | DE2430784B2 (enExample) |
| FR (1) | FR2276655A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3004565A1 (de) * | 1980-02-07 | 1981-08-13 | Siemens AG, 1000 Berlin und 8000 München | Integrierte digitale halbleiterschaltung |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5341968A (en) * | 1976-09-29 | 1978-04-15 | Hitachi Ltd | Semiconductor circuit |
| US4162541A (en) * | 1977-02-17 | 1979-07-24 | Xerox Corporation | Apparatus for overscribing binary data of a selected polarity into a semiconductor store |
| US4142112A (en) * | 1977-05-06 | 1979-02-27 | Sperry Rand Corporation | Single active element controlled-inversion semiconductor storage cell devices and storage matrices employing same |
| JPS5841596B2 (ja) * | 1980-11-28 | 1983-09-13 | 富士通株式会社 | スタティック型半導体記憶装置 |
| US4855803A (en) * | 1985-09-02 | 1989-08-08 | Ricoh Company, Ltd. | Selectively definable semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1482050A (fr) * | 1966-03-08 | 1967-05-26 | Labo Cent Telecommunicat | Mémoire matricielle en circuits intégrés |
| US3786442A (en) * | 1972-02-24 | 1974-01-15 | Cogar Corp | Rapid recovery circuit for capacitively loaded bit lines |
-
1974
- 1974-06-26 DE DE19742430784 patent/DE2430784B2/de active Granted
-
1975
- 1975-06-04 US US05/583,690 patent/US4005393A/en not_active Expired - Lifetime
- 1975-06-25 FR FR7519915A patent/FR2276655A1/fr active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3004565A1 (de) * | 1980-02-07 | 1981-08-13 | Siemens AG, 1000 Berlin und 8000 München | Integrierte digitale halbleiterschaltung |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2276655B1 (enExample) | 1982-02-12 |
| DE2430784A1 (de) | 1976-01-15 |
| FR2276655A1 (fr) | 1976-01-23 |
| US4005393A (en) | 1977-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE3041176C2 (enExample) | ||
| DE4035660C2 (de) | Elektrisch programmierbare Speichereinrichtung und Verfahren zum Zugreifen/Programmieren von Speicherzellen | |
| DE3305056C2 (de) | Halbleiterspeicher | |
| DE69129138T2 (de) | DRAM mit einem Wortleitungsbetriebsschaltungssystem | |
| DE2556831C2 (de) | Matrixspeicher und Verfahren zu seinem Betrieb | |
| DE3148806C2 (enExample) | ||
| DE2731442C2 (de) | Speicherschaltung mit Isolierschicht-Feldeffekttransistoren | |
| DE69900191T2 (de) | Vorrichtung und Verfahren zum Trimmen einer nichtflüchtigen Halbleiterspeicheranordnung ohne irgendwelche überflüssigen Kontaktflächen oder Stifte | |
| DE102005053717A1 (de) | Erfass-Verstärker-Bitleitungs-Verstärkungs-Schaltkreis | |
| DE2303409A1 (de) | Monolithisch integrierbare speicheranordnung | |
| DE19625169A1 (de) | Hierarchische Wortleitungsstruktur für Halbleiterspeichervorrichtung | |
| DE3234409A1 (de) | Dynamische metalloxidschicht-halbleiterspeichervorrichtung | |
| DE2712735B1 (de) | Lese-/Schreibzugriffschaltung zu Speicherzellen eines Speichers und Verfahren zu ihrem Betrieb | |
| DE69028616T2 (de) | Nichtflüchtiger Halbleiterspeicher in dem Blindzellen verwendet werden, um eine Spannung zu erzeugen, während Daten gelesen werden | |
| DE2646653C3 (enExample) | ||
| DE2620749B2 (de) | Matrixspeicher aus halbleiterelementen | |
| DE2430784B2 (de) | Bipolarer halbleiterspeicher | |
| DE2835692B2 (de) | Binäres logisches ODER-Glied für programmierte logische Anordnungen | |
| EP0078338A1 (de) | FET-Speicher | |
| DE1524900A1 (de) | Bistabile Schaltungsanordnung mit zwei Transistoren | |
| DE2360378A1 (de) | Speicherzelle | |
| DE3917558A1 (de) | Halbleiterspeichereinrichtung | |
| DE3132082C2 (enExample) | ||
| DE3424760C2 (de) | Statische Speicherzelle mit elektrisch programmierbarem, nichtflüchtigem Speicherelement | |
| DE69125576T2 (de) | Speicheranordnung mit Abtastverstärkern vom Stromspiegeltyp |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C3 | Grant after two publication steps (3rd publication) | ||
| E77 | Valid patent as to the heymanns-index 1977 |