DE2425684A1 - Verfahren zum aetzen von silicium enthaltenden materialien - Google Patents

Verfahren zum aetzen von silicium enthaltenden materialien

Info

Publication number
DE2425684A1
DE2425684A1 DE19742425684 DE2425684A DE2425684A1 DE 2425684 A1 DE2425684 A1 DE 2425684A1 DE 19742425684 DE19742425684 DE 19742425684 DE 2425684 A DE2425684 A DE 2425684A DE 2425684 A1 DE2425684 A1 DE 2425684A1
Authority
DE
Germany
Prior art keywords
etching
melt
temperature
sio
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19742425684
Other languages
German (de)
English (en)
Inventor
Marian Dipl Chem Briska
Wolfgang Dipl Chem Hoffmeister
Herbert Kuhlmey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IBM Deutschland GmbH
Original Assignee
IBM Deutschland GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IBM Deutschland GmbH filed Critical IBM Deutschland GmbH
Priority to DE19742425684 priority Critical patent/DE2425684A1/de
Priority to US05/570,068 priority patent/US3971683A/en
Priority to FR7513743A priority patent/FR2273081B1/fr
Priority to JP50053326A priority patent/JPS50153795A/ja
Priority to GB2047575A priority patent/GB1475656A/en
Publication of DE2425684A1 publication Critical patent/DE2425684A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Surface Treatment Of Glass (AREA)
  • Silicon Compounds (AREA)
  • Weting (AREA)
DE19742425684 1974-05-28 1974-05-28 Verfahren zum aetzen von silicium enthaltenden materialien Withdrawn DE2425684A1 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE19742425684 DE2425684A1 (de) 1974-05-28 1974-05-28 Verfahren zum aetzen von silicium enthaltenden materialien
US05/570,068 US3971683A (en) 1974-05-28 1975-04-21 Method of etching materials containing silicon
FR7513743A FR2273081B1 (US06174465-20010116-C00003.png) 1974-05-28 1975-04-24
JP50053326A JPS50153795A (US06174465-20010116-C00003.png) 1974-05-28 1975-05-06
GB2047575A GB1475656A (en) 1974-05-28 1975-05-15 Method of etching materials containing silicon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19742425684 DE2425684A1 (de) 1974-05-28 1974-05-28 Verfahren zum aetzen von silicium enthaltenden materialien

Publications (1)

Publication Number Publication Date
DE2425684A1 true DE2425684A1 (de) 1975-12-11

Family

ID=5916629

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19742425684 Withdrawn DE2425684A1 (de) 1974-05-28 1974-05-28 Verfahren zum aetzen von silicium enthaltenden materialien

Country Status (5)

Country Link
US (1) US3971683A (US06174465-20010116-C00003.png)
JP (1) JPS50153795A (US06174465-20010116-C00003.png)
DE (1) DE2425684A1 (US06174465-20010116-C00003.png)
FR (1) FR2273081B1 (US06174465-20010116-C00003.png)
GB (1) GB1475656A (US06174465-20010116-C00003.png)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007054484B3 (de) * 2007-11-15 2009-03-12 Deutsche Cell Gmbh Strukturier-Verfahren

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339349A (en) * 1976-09-24 1978-04-11 Asahi Glass Co Ltd Thermosetting resin molding material
JPS5370688A (en) * 1976-12-06 1978-06-23 Toshiba Corp Production of semoconductor device
US4283248A (en) * 1979-02-01 1981-08-11 Nitto Electric Industrial Co., Ltd. Etching solution for tin-nickel alloy and process for etching the same
US4465550A (en) * 1982-06-16 1984-08-14 General Signal Corporation Method and apparatus for slicing semiconductor ingots
US4713145A (en) * 1986-12-19 1987-12-15 Gulton Industries, Inc. Method of etching etch-resistant materials
DE4414925A1 (de) * 1994-04-28 1995-11-02 Wacker Chemitronic Verfahren zur Behandlung von Halbleitermaterial mit einer säurehaltigen Flüssigkeit
US6117351A (en) * 1998-04-06 2000-09-12 Micron Technology, Inc. Method for etching dielectric films
US6286685B1 (en) * 1999-03-15 2001-09-11 Seh America, Inc. System and method for wafer thickness sorting
JP2006509229A (ja) * 2002-12-03 2006-03-16 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ ディスプレイの製造方法
US20040226506A1 (en) * 2003-05-14 2004-11-18 Lynn David Mark Coated wafer processing equipment
JP4746413B2 (ja) * 2005-11-28 2011-08-10 大王製紙株式会社 体液吸収性物品
JP6433730B2 (ja) * 2014-09-08 2018-12-05 東芝メモリ株式会社 半導体装置の製造方法及び半導体製造装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3715249A (en) * 1971-09-03 1973-02-06 Bell Telephone Labor Inc Etching si3n4
GB1423448A (en) * 1973-07-18 1976-02-04 Plessey Co Ltd Method of selectively etching silicon nitride

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007054484B3 (de) * 2007-11-15 2009-03-12 Deutsche Cell Gmbh Strukturier-Verfahren
US8182710B2 (en) 2007-11-15 2012-05-22 Deutsche Cell Gmbh Structuring method

Also Published As

Publication number Publication date
US3971683A (en) 1976-07-27
JPS50153795A (US06174465-20010116-C00003.png) 1975-12-11
FR2273081B1 (US06174465-20010116-C00003.png) 1977-07-22
GB1475656A (en) 1977-06-01
FR2273081A1 (US06174465-20010116-C00003.png) 1975-12-26

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Legal Events

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8139 Disposal/non-payment of the annual fee