DE2313219B2 - Verfahren zur Herstellung einer Halbleiteranordnung mit einer auf mehreren Niveaus liegenden Metallisierung - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung mit einer auf mehreren Niveaus liegenden Metallisierung

Info

Publication number
DE2313219B2
DE2313219B2 DE2313219A DE2313219A DE2313219B2 DE 2313219 B2 DE2313219 B2 DE 2313219B2 DE 2313219 A DE2313219 A DE 2313219A DE 2313219 A DE2313219 A DE 2313219A DE 2313219 B2 DE2313219 B2 DE 2313219B2
Authority
DE
Germany
Prior art keywords
electrically conductive
layer
dielectric layer
openings
sections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE2313219A
Other languages
German (de)
English (en)
Other versions
DE2313219A1 (de
Inventor
Carl Neil Warren Township Berglund
Edward Haig Murray Hill Nicollian
Michael Francis Summit Tompsett
Herbert Atkin Allentown Pa. Waggener
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of DE2313219A1 publication Critical patent/DE2313219A1/de
Publication of DE2313219B2 publication Critical patent/DE2313219B2/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00—Charge transfer devices
    • H10D44/01—Manufacture or treatment
    • H10D44/041—Manufacture or treatment having insulated gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00—Charge transfer devices
    • H10D44/40—Charge-coupled devices [CCD]
    • H10D44/45—Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/43—Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/944—Shadow

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
DE2313219A 1972-03-22 1973-03-16 Verfahren zur Herstellung einer Halbleiteranordnung mit einer auf mehreren Niveaus liegenden Metallisierung Ceased DE2313219B2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00236886A US3837907A (en) 1972-03-22 1972-03-22 Multiple-level metallization for integrated circuits

Publications (2)

Publication Number Publication Date
DE2313219A1 DE2313219A1 (de) 1973-10-04
DE2313219B2 true DE2313219B2 (de) 1979-07-05

Family

ID=22891400

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2313219A Ceased DE2313219B2 (de) 1972-03-22 1973-03-16 Verfahren zur Herstellung einer Halbleiteranordnung mit einer auf mehreren Niveaus liegenden Metallisierung

Country Status (5)

Country Link
US (1) US3837907A (enExample)
JP (1) JPS498189A (enExample)
DE (1) DE2313219B2 (enExample)
FR (1) FR2176996B1 (enExample)
GB (1) GB1401560A (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3994758A (en) * 1973-03-19 1976-11-30 Nippon Electric Company, Ltd. Method of manufacturing a semiconductor device having closely spaced electrodes by perpendicular projection
US3967306A (en) * 1973-08-01 1976-06-29 Trw Inc. Asymmetrical well charge coupled device
US3924319A (en) * 1974-08-12 1975-12-09 Bell Telephone Labor Inc Method of fabricating stepped electrodes
US3898353A (en) * 1974-10-03 1975-08-05 Us Army Self aligned drain and gate field effect transistor
US3957552A (en) * 1975-03-05 1976-05-18 International Business Machines Corporation Method for making multilayer devices using only a single critical masking step
US4076575A (en) * 1976-06-30 1978-02-28 International Business Machines Corporation Integrated fabrication method of forming connectors through insulative layers
US4101731A (en) * 1976-08-20 1978-07-18 Airco, Inc. Composite multifilament superconductors
JPS5370688A (en) * 1976-12-06 1978-06-23 Toshiba Corp Production of semoconductor device
US4098638A (en) * 1977-06-14 1978-07-04 Westinghouse Electric Corp. Methods for making a sloped insulator for solid state devices
US4149307A (en) * 1977-12-28 1979-04-17 Hughes Aircraft Company Process for fabricating insulated-gate field-effect transistors with self-aligned contacts
US4176029A (en) * 1978-03-02 1979-11-27 Sperry Rand Corporation Subminiature bore and conductor formation
IT1094517B (it) * 1978-04-28 1985-08-02 Componenti Elettronici Sgs Ate Procedimento per la fabbricazione di un elemento resistivo filiforme per circuito integrato
US4262399A (en) * 1978-11-08 1981-04-21 General Electric Co. Ultrasonic transducer fabricated as an integral park of a monolithic integrated circuit
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process
NL8202777A (nl) * 1982-07-09 1984-02-01 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen daarvan.
JPH0759441B2 (ja) * 1990-11-21 1995-06-28 東和工業株式会社 粗糸ボビンの貯留装置
JP2642523B2 (ja) * 1991-03-19 1997-08-20 株式会社東芝 電荷結合素子を持つ半導体集積回路装置の製造方法
US5688474A (en) * 1993-06-01 1997-11-18 Eduardo E. Wolf Device for treating gases using microfabricated matrix of catalyst
US5976970A (en) * 1996-03-29 1999-11-02 International Business Machines Corporation Method of making and laterally filling key hole structure for ultra fine pitch conductor lines
US5981374A (en) * 1997-04-29 1999-11-09 International Business Machines Corporation Sub-half-micron multi-level interconnection structure and process thereof
US6133139A (en) 1997-10-08 2000-10-17 International Business Machines Corporation Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof
US6365489B1 (en) 1999-06-15 2002-04-02 Micron Technology, Inc. Creation of subresolution features via flow characteristics
ES2585058T3 (es) * 2012-05-21 2016-10-03 Danmarks Tekniske Universitet Método para producir sustratos para capas superconductoras
US10814609B2 (en) * 2016-03-17 2020-10-27 Massachusetts Institute Of Technology Systems and methods for selectively coating a substrate using shadowing features
EP4118465A4 (en) 2020-03-11 2024-03-13 Labforinvention ENERGY EFFICIENT WINDOW COVERINGS
WO2022150832A1 (en) 2021-01-08 2022-07-14 LabForInvention Window coating transmissible to wireless communication signals
US11587895B2 (en) 2021-04-21 2023-02-21 Micron Technology, Inc. Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods
US12370779B2 (en) 2023-08-28 2025-07-29 LabForInvention Energy-efficient window coatings transmittable to wireless communication signals and methods of fabricating thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1614829C3 (de) * 1967-06-22 1974-04-04 Telefunken Patentverwertungs Gmbh, 7900 Ulm Verfahren zum Herstellen eines Halbleiterbauelementes
US3681134A (en) * 1968-05-31 1972-08-01 Westinghouse Electric Corp Microelectronic conductor configurations and methods of making the same
NL6906939A (enExample) * 1969-05-06 1970-11-10
US3651349A (en) * 1970-02-16 1972-03-21 Bell Telephone Labor Inc Monolithic semiconductor apparatus adapted for sequential charge transfer
US3678573A (en) * 1970-03-10 1972-07-25 Westinghouse Electric Corp Self-aligned gate field effect transistor and method of preparing
US3716429A (en) * 1970-06-18 1973-02-13 Rca Corp Method of making semiconductor devices
US3675313A (en) * 1970-10-01 1972-07-11 Westinghouse Electric Corp Process for producing self aligned gate field effect transistor
US3676230A (en) * 1971-02-16 1972-07-11 Trw Inc Method for fabricating semiconductor junctions
US3700469A (en) * 1971-03-08 1972-10-24 Bell Telephone Labor Inc Electroless gold plating baths

Also Published As

Publication number Publication date
FR2176996A1 (enExample) 1973-11-02
JPS498189A (enExample) 1974-01-24
GB1401560A (en) 1975-07-16
US3837907A (en) 1974-09-24
DE2313219A1 (de) 1973-10-04
FR2176996B1 (enExample) 1977-07-29

Similar Documents

Publication Publication Date Title
DE2313219B2 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit einer auf mehreren Niveaus liegenden Metallisierung
DE2945533C2 (de) Verfahren zur Herstellung eines Verdrahtungssystems
DE69122436T2 (de) Verfahren zum Herstellen einer Stufe in einer integrierten Schaltung
DE68923305T2 (de) Elektrische Leitungen für elektronische Bauelemente.
DE2212049C2 (de) Verfahren zur Herstellung einer Halbleiteranordnung und Verfahren zur Herstellung eines Transistors
DE2646308C3 (de) Verfahren zum Herstellen nahe beieinander liegender elektrisch leitender Schichten
DE2729030C2 (de) Verfahren zum Herstellen eines mehrschichtigen Leiterzugsmusters für monolithisch integrierte Halbleiterschaltungen
DE2430692C2 (de) Verfahren zum Herstellen von Verbindungslöchern in Isolierschichten
DE1930669C2 (de) Verfahren zur Herstellung einer integrierten Halbleiterschaltung
DE2319883A1 (de) Verfahren zur herstellung einer halbleiteranordnung mit einem leitermuster und durch dieses verfahren hergestellte anordnung
DE3311635A1 (de) Halbleiterbauelement und verfahren zu dessen herstellung
DE2502235A1 (de) Ladungskopplungs-halbleiteranordnung
DE3024084A1 (de) Verfahren zur herstellung von halbleiterbauelementen
DE1690509B1 (de) Verfahren zur bildung zweier eng voneinandergetrennter leitender schichten
DE2723944A1 (de) Anordnung aus einer strukturierten schicht und einem muster festgelegter dicke und verfahren zu ihrer herstellung
DE19501557A1 (de) Halbleitervorrichtung und Verfahren zu deren Herstellung
DE2734176A1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE2922015A1 (de) Verfahren zur herstellung einer vlsi-schaltung
DE2636971A1 (de) Verfahren zum herstellen einer isolierenden schicht mit ebener oberflaeche auf einem substrat
DE69022637T2 (de) Verfahren zur Herstellung eines Halbleiterbauelementes auf welchem eine isolierende Shicht eine gleichmässige Dicke hat.
DE69404593T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung, die einen Halbleiterkörper mit Feldisolierungszonen aus mit Isolierstoff gefüllten Graben enthält
DE1924712C3 (de) Integrierter Dünnschicht-Abblockbzw. Entkopplungskondensator für monolithische Schaltungen und Verfahren zu seiner Herstellung
DE2132034A1 (de) Verfahren zur Herstellung von Zwischenverbindungen fuer elektrische Baueinheiten auf Festkoerpern
DE10246682A1 (de) Halbleiter-Vorrichtung
DE1589076C3 (de) Verfahren zum Herstellen von Halbleiteranordnungen mit tragfähigen elektrischen Leitern

Legal Events

Date Code Title Description
8235 Patent refused