DE69022637T2 - Verfahren zur Herstellung eines Halbleiterbauelementes auf welchem eine isolierende Shicht eine gleichmässige Dicke hat. - Google Patents
Verfahren zur Herstellung eines Halbleiterbauelementes auf welchem eine isolierende Shicht eine gleichmässige Dicke hat.Info
- Publication number
- DE69022637T2 DE69022637T2 DE69022637T DE69022637T DE69022637T2 DE 69022637 T2 DE69022637 T2 DE 69022637T2 DE 69022637 T DE69022637 T DE 69022637T DE 69022637 T DE69022637 T DE 69022637T DE 69022637 T2 DE69022637 T2 DE 69022637T2
- Authority
- DE
- Germany
- Prior art keywords
- producing
- insulating layer
- uniform thickness
- semiconductor component
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/133—Reflow oxides and glasses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1169070A JP2556138B2 (ja) | 1989-06-30 | 1989-06-30 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69022637D1 DE69022637D1 (de) | 1995-11-02 |
DE69022637T2 true DE69022637T2 (de) | 1996-03-21 |
Family
ID=15879770
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69022637T Expired - Lifetime DE69022637T2 (de) | 1989-06-30 | 1990-07-02 | Verfahren zur Herstellung eines Halbleiterbauelementes auf welchem eine isolierende Shicht eine gleichmässige Dicke hat. |
Country Status (4)
Country | Link |
---|---|
US (1) | US5169801A (de) |
EP (1) | EP0406025B1 (de) |
JP (1) | JP2556138B2 (de) |
DE (1) | DE69022637T2 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5285102A (en) * | 1991-07-25 | 1994-02-08 | Texas Instruments Incorporated | Method of forming a planarized insulation layer |
JPH0541457A (ja) * | 1991-08-06 | 1993-02-19 | Nec Corp | 半導体装置の製造方法 |
US5414221A (en) * | 1991-12-31 | 1995-05-09 | Intel Corporation | Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias |
US5323047A (en) * | 1992-01-31 | 1994-06-21 | Sgs-Thomson Microelectronics, Inc. | Structure formed by a method of patterning a submicron semiconductor layer |
JPH05235184A (ja) * | 1992-02-26 | 1993-09-10 | Nec Corp | 半導体装置の多層配線構造体の製造方法 |
DE69424388T2 (de) * | 1993-12-23 | 2000-08-31 | St Microelectronics Inc | Verfahren und Dielektrikumstruktur zur Erleichterung der Metallüberätzung ohne Beschädigung des Zwischendielektrikums |
US5449644A (en) * | 1994-01-13 | 1995-09-12 | United Microelectronics Corporation | Process for contact hole formation using a sacrificial SOG layer |
US5565381A (en) * | 1994-08-01 | 1996-10-15 | Microchip Technology Incorporated | Method of removing sharp edges in a dielectric coating located above a semiconductor substrate and a semiconductor device formed by this method |
US5413953A (en) * | 1994-09-30 | 1995-05-09 | United Microelectronics Corporation | Method for planarizing an insulator on a semiconductor substrate using ion implantation |
US5554560A (en) * | 1994-09-30 | 1996-09-10 | United Microelectronics Corporation | Method for forming a planar field oxide (fox) on substrates for integrated circuit |
JP3402022B2 (ja) * | 1995-11-07 | 2003-04-28 | 三菱電機株式会社 | 半導体装置の製造方法 |
US6169026B1 (en) | 1995-11-20 | 2001-01-02 | Hyundai Electronics Industries Co., Ltd. | Method for planarization of semiconductor device including pumping out dopants from planarization layer separately from flowing said layer |
US5817571A (en) * | 1996-06-10 | 1998-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multilayer interlevel dielectrics using phosphorus-doped glass |
US5973385A (en) * | 1996-10-24 | 1999-10-26 | International Business Machines Corporation | Method for suppressing pattern distortion associated with BPSG reflow and integrated circuit chip formed thereby |
DE19829152A1 (de) * | 1998-05-05 | 1999-11-18 | United Microelectronics Corp | Doppeltes Damaszierverfahren |
JP4943833B2 (ja) * | 2006-12-27 | 2012-05-30 | シャープ株式会社 | 空気調和機 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2040180B2 (de) * | 1970-01-22 | 1977-08-25 | Intel Corp, Mountain View, Calif. (V.St.A.) | Verfahren zur verhinderung von mechanischen bruechen einer duennen, die oberflaeche eines halbleiterkoerpers ueberdeckende isolierschichten ueberziehenden elektrisch leitenden schicht |
US4355454A (en) * | 1979-09-05 | 1982-10-26 | Texas Instruments Incorporated | Coating device with As2 -O3 -SiO2 |
US4489481A (en) * | 1982-09-20 | 1984-12-25 | Texas Instruments Incorporated | Insulator and metallization method for VLSI devices with anisotropically-etched contact holes |
JPS60173856A (ja) * | 1984-02-10 | 1985-09-07 | Fujitsu Ltd | 半導体装置の製造方法 |
KR900004968B1 (ko) * | 1984-02-10 | 1990-07-12 | 후지쓰 가부시끼가이샤 | 반도체장치 제조방법 |
US4743564A (en) * | 1984-12-28 | 1988-05-10 | Kabushiki Kaisha Toshiba | Method for manufacturing a complementary MOS type semiconductor device |
JPH0693456B2 (ja) * | 1985-03-26 | 1994-11-16 | ソニー株式会社 | 半導体装置の製造方法 |
US4605470A (en) * | 1985-06-10 | 1986-08-12 | Advanced Micro Devices, Inc. | Method for interconnecting conducting layers of an integrated circuit device |
JPS621246A (ja) * | 1985-06-26 | 1987-01-07 | Nec Corp | 半導体装置およびその製造方法 |
US4741926A (en) * | 1985-10-29 | 1988-05-03 | Rca Corporation | Spin-coating procedure |
US4753866A (en) * | 1986-02-24 | 1988-06-28 | Texas Instruments Incorporated | Method for processing an interlevel dielectric suitable for VLSI metallization schemes |
JP2605686B2 (ja) * | 1986-04-10 | 1997-04-30 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US4775550A (en) * | 1986-06-03 | 1988-10-04 | Intel Corporation | Surface planarization method for VLSI technology |
US4676867A (en) * | 1986-06-06 | 1987-06-30 | Rockwell International Corporation | Planarization process for double metal MOS using spin-on glass as a sacrificial layer |
US4708770A (en) * | 1986-06-19 | 1987-11-24 | Lsi Logic Corporation | Planarized process for forming vias in silicon wafers |
JPS6386546A (ja) * | 1986-09-30 | 1988-04-16 | Pioneer Electronic Corp | 多重配線基板の製造方法 |
JPS6386545A (ja) * | 1986-09-30 | 1988-04-16 | Pioneer Electronic Corp | 多層配線基板の製造方法 |
JPS6386547A (ja) * | 1986-09-30 | 1988-04-16 | Pioneer Electronic Corp | 多重配線基板の製造方法 |
US4885262A (en) * | 1989-03-08 | 1989-12-05 | Intel Corporation | Chemical modification of spin-on glass for improved performance in IC fabrication |
-
1989
- 1989-06-30 JP JP1169070A patent/JP2556138B2/ja not_active Expired - Lifetime
-
1990
- 1990-07-02 DE DE69022637T patent/DE69022637T2/de not_active Expired - Lifetime
- 1990-07-02 EP EP90307188A patent/EP0406025B1/de not_active Expired - Lifetime
-
1991
- 1991-12-31 US US07/816,841 patent/US5169801A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0406025B1 (de) | 1995-09-27 |
EP0406025A3 (de) | 1991-02-27 |
US5169801A (en) | 1992-12-08 |
JPH0334546A (ja) | 1991-02-14 |
DE69022637D1 (de) | 1995-11-02 |
EP0406025A2 (de) | 1991-01-02 |
JP2556138B2 (ja) | 1996-11-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC CORP., TOKIO/TOKYO, JP Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: ELPIDA MEMORY, INC., TOKYO, JP |